Non-contiguous masked refresh for an integrated circuit memory

Details Non-contiguous masked refresh for an integrated circuit memory Non-contiguous masked refresh for an integrated circuit memory

2005-06-28

2005-06-28

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S189070, C365S191000, C365S230010, C365S230080

Reexamination Certificate

active

06912168

ABSTRACT:
A refresh circuit is used for refreshing or masking from refresh non-contiguous subarrays in an integrated circuit memory array. At the initiation of each masked refresh cycle the address inputs, which normally are ignored, are evaluated to indicate which subarrays should be refreshed and which should be not refreshed. Power is saved due to the flexibility in determining which subarrays are refreshed at each new refresh cycle.

REFERENCES:
patent: 6049497 (2000-04-01), Yero
patent: 6646941 (2003-11-01), Atwell et al.
128-Mbit Synchronous Low-Power DRAM in Chipsize Packages, Infineon Technologies, HYB/E 25L128160AC, 128-MBit Mobile-RAM, Dec. 2001, pp. 1-49.

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