Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-07-11
2006-07-11
Decady, Albert (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S718000, C714S733000, C714S702000, C365S201000
Reexamination Certificate
active
07076710
ABSTRACT:
Method and system for testing a memory array having a non-uniform binary address space. The test system includes a test engine for generating addresses for the memory array and for generating and applying data patterns to the memory array. The test engine has an address generator including a series combination of a linear register and a binary counter for generating the non-uniform address.
REFERENCES:
patent: 5222109 (1993-06-01), Pricer
patent: 5633877 (1997-05-01), Shephard et al.
patent: 6829181 (2004-12-01), Seitoh
patent: 2002/0194557 (2002-12-01), Park
Chang Tom Y.
Dawson James W.
Knips Thomas J.
Malone Douglas J.
Augspurger Lynn L.
De'cady Albert
Gandhi Dipakkumar
Goldman Richard M.
International Business Machines - Corporation
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