Noise restraining semiconductor memory device

Details Noise restraining semiconductor memory device Noise restraining semiconductor memory device

1997-11-13

1999-04-27

Mai, Son

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365191, G11C 700

Patent

active

058986243

ABSTRACT:
A noise restraining semiconductor memory device includes a memory cell array for outputting through a data line a complementary cell data signal selected in accordance with an input address signal, an output controller for combining a data output enable signal and a Y address latch signal and generating a data output control signal, and an output buffer for buffering and outputting to an input/output pin a data signal outputted from the memory cell array in accordance with the output control signal outputted from the output controller. The memory device makes an operation start time of the output buffer delayed later than a time point in which an output data signal of the memory cell is latched to an input terminal of the output buffer, thereby excluding ground noise.

REFERENCES:
patent: 5311471 (1994-05-01), Matsumoto et al.
patent: 5444666 (1995-08-01), Oh
patent: 5652724 (1997-07-01), Manning

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