Noise-resistive, burst-mode receiving apparatus and a method...

Details Noise-resistive, burst-mode receiving apparatus and a method... Noise-resistive, burst-mode receiving apparatus and a method...

2007-02-13

2007-02-13

Ghayour, Mohammed (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S354000, C375S371000, C375S373000, C455S260000, C324S076530, C327S147000, C327S156000, C713S322000

Reexamination Certificate

active

10179400

ABSTRACT:
A noise-resistive, burst-mode receiving apparatus including a voltage control signal generator for multiplying a frequency of a system clock signal and generating a voltage control signal having a level that corresponds to the multiplied frequency; a reset signal generator for delaying an irregular input signal in the unit of a packet, in response to the voltage control signal, performing an exclusive OR operation on the delayed and input signals, and outputting the result as a reset signal; a clock signal generator for generating a signal having a level that is changed at the middle point of each bit included in the packet as a recovered clock signal in response to the reset signal and the voltage control signal and outputting the recovered clock signal; and an output buffer for buffering the input signal and outputting the buffered signal as recovered data in response to the recovered clock signal.

REFERENCES:
patent: 4513427 (1985-04-01), Borriello et al.
patent: 5319266 (1994-06-01), Chu et al.
patent: 5399995 (1995-03-01), Kardontchik et al.
patent: 5432827 (1995-07-01), Mader
patent: 6236697 (2001-05-01), Fang

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