NMOS input receiver circuit

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

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Details

365226, 36523008, G11C 1604, G11C 700, G11C 800

Patent

active

060026189

ABSTRACT:
An input receiver circuit in a read-only memory is provided with a feedback to control hysteresis. A second stage and an additional output is added to the receiver. Switching circuit noise from inside of the read-only memory is isolated by the added state and outputs, and cannot be fed back into the receiver circuit to affect the detection of the TTL voltage levels. Use of wide and long FET sizes minimizes the manufacture related variations in the input receiver switching levels.

REFERENCES:
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patent: 4786830 (1988-11-01), Foss
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patent: 5079439 (1992-01-01), Wanlass
patent: 5144167 (1992-09-01), McClintock
patent: 5151620 (1992-09-01), Lin
patent: 5151622 (1992-09-01), Thrower et al.
patent: 5304867 (1994-04-01), Morris

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