Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-07-30
2002-04-09
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S610000
Reexamination Certificate
active
06369434
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the manufacture of semiconductor devices. In particular, the present invention relates to a process for forming p-type metal oxide semiconductor field effect transistors (pMOSFETs) with shallow junction extensions.
BACKGROUND OF THE INVENTION
An “TET” is a Field Effect Transistor. There are two major types of FET's, the metal-oxide-semiconductor field effect transistor or MOSFET (also called an insulated-gate FET, or IGFET), and the junction-gate FET, or JFET. An FET has a control gate, and source and drain regions formed in a substrate. The control gate is formed above a dielectric insulator that is deposited over the area between the source and drain regions. As voltage is applied to the control gate, mobile charged particles in the substrate form a conduction channel in the region between the source and drain regions. Once the channel forms, the transistor turns “on” and current may flow between the source and drain regions.
A MOSFET is a three-terminal device that is used to control the flow of electric power. MOSFETs have only three semiconductor regions. A MOSFET controls the flow of power through the device in response to an appropriate control signal applied to its gate terminal. MOSFETs can be used to control the flow of electric power by selectively applying and removing an appropriate gate signal.
Very Large Scale Integration or “VLSI” (i.e., more than 100,000 devices per chip) has allowed the semiconductor chip industry to increase circuit density while still maintaining or even reducing cost. This advantage has been accomplished because the semiconductor industry can now fabricate silicon devices with sub-micron features (or micro-miniaturization). The attainment of sub-micron features has been achieved mainly by advances in specific semiconductor fabrication disciplines, such as photolithography and reactive ion etching (RIE).
“Photolithography” is a process in which a light source illuminates a circuit pattern and projects the image through a lens assembly onto a semiconductor wafer or substrate. Ultimately, the circuit pattern is etched into the wafer. The use of more sophisticated exposure cameras and the development of more sensitive photoresist materials have allowed sub-micron images in photoresist to be routinely obtained. Similar advances in dry etching tools and processes have resulted in the successful transfer of these sub-micron images in photoresist to underlying materials used for the fabrication of advanced CMOS (complimentary metal oxide semiconductor) devices.
With the trend to smaller devices, however, specific yield and performance detractors, as well as reliability risks, become more prevalent. For example, as the gate insulator of a CMOS device becomes thinner, in an attempt to improve device performance, the possibility of yield loss due to insulator breakdown becomes greater. In addition, as the channel length of the CMOS device becomes shorter, again to improve performance, the reliability risk of hot electron injection increases. Narrower channel lengths also present yield problems in terms of junction punch-through. As the channel length of a CMOS device shortens, the space between depletion regions, created from the source region and the substrate and from the drain region and substrate, becomes smaller and the consequent close proximity of adjacent regions can result in punch-through leakage.
CMOS circuits are made up of complementary pairs of nMOSFETs and pMOSFETs. MOSFETs can be classified into two types having different electrical polarities, i.e., negative MOSFETs (nMOSFETs) in which electrons flow through a channel region and positive MOSFETs (pMOSFETs) in which holes flow through a channel region. nMOSFETs and pMOSFETs are combined to form various kinds of circuits. NMOS refers to circuits made entirely of nMOSFETs.
The p-type region is typically formed by ion implantation of boron atoms. Ion implantation is a well-known technique that consists of bombarding the surface of the silicon with high energy ions in a vacuum. The ions penetrate into the silicon, to a depth depending on their energy, and, after an annealing treatment to remove lattice dislocations, convert a thin layer of silicon to p-type silicon. Because boron atoms have a small mass and a large diffusion coefficient, they have a strong tendency to diffuse at the temperatures used during a later heat treatment.
A pMOSFET of 0.15 microns or less requires a shallow p-junction extension (Pext) of 40 nm or less. When boron is used as the dopant in the formation of the junction extension of a pMOSFET, the large diffusion coefficient of boron makes it difficult to form a shallow Pext by traditional methods, such as by lowering the implantation energy or reducing the rapid thermal annealing (RTA) time or temperature because of the strong tendency of boron atoms to diffuse at high temperatures. For example, with an RTA of 1,000° C. for 5 seconds, the shallowest Pext that can be achieved is still much deeper than 50 nm. As the size of the FET shrinks, however, there is a need to make precisely controlled shallow Pexts reliably while avoiding device failures due to punch-through effects.
The need for the ability to make shallow Pexts has been recognized by the industry. One method for solving this problem is disclosed in U.S. Pat. No. 5,557,129 issued to Oda. This patent describes formation of an ultra shallow p-junction extension by an FET structure that includes a spacer comprising a vertical and a horizontal component surrounding the FET gate and extending about 1,000 to 3,000 Å from the gate. Such a structure introduces additional masking steps to the process of manufacturing the FET without addressing the problem of boron migration directly. Shallower Pext improves threshold voltage roll off, a key MOSFET design issue for deep sub-micron devices.
Thus, a need exists for a reliable process for forming pMOSFETs in which boron diffusion during thermal treatments does not adversely affect the p-junction shallow extensions.
SUMMARY OF THE INVENTION
To meet this and other needs, and in view of its purposes, the present invention provides a process for making a p-type field effect transistor. The process of the present invention comprises forming a gate on a substrate and forming a drain and a source in the substrate by doping the substrate with boron to form p-doped junction extensions. A containment layer is formed in the substrate extending from a surface of the substrate to a predetermined depth, exclusive of an area of the substrate under the gate. The containment layer consists essentially of implanted nitrogen, a p-type dopant, and a substrate selected from the group consisting of germanium and silicon.
The present invention also provides a semiconductor device with a substrate comprising a substrate material selected from the group consisting of silicon and germanium. An element is provided over the substrate defining a first area on the substrate and a containment layer in the substrate outside the defined first area. The containment layer consists essentially of implanted nitrogen, a p-type dopant, and the substrate material.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
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Chen Kai
Crowder Scott W.
Han Liang-Kai
Hargrove Michael J.
Lee Kam-Leung
Abate Esq. Joseph P.
Abraham Fetsum
Ratner & Prestia
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