Nitride semiconductor structures with interlayer structures

Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – With lattice constant mismatch

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S096000, C257SE33003

Reexamination Certificate

active

07825432

ABSTRACT:
A semiconductor structure includes a first layer of a nitride semiconductor material, a substantially unstrained nitride interlayer on the first layer of nitride semiconductor material, and a second layer of a nitride semiconductor material on the nitride interlayer. The nitride interlayer has a first lattice constant and may include aluminum and gallium and may be conductively doped with an n-type dopant. The first layer and the second layer together have a thickness of at least about 0.5 μm. The nitride semiconductor material may have a second lattice constant, such that the first layer may be more tensile strained on one side of the nitride interlayer than the second layer may be on the other side of the nitride interlayer.

REFERENCES:
patent: 34861 (1862-04-01), Knowlton
patent: 4946547 (1990-08-01), Palmour et al.
patent: 5072122 (1991-12-01), Jiang et al.
patent: 5101109 (1992-03-01), Jiang et al.
patent: 5200022 (1993-04-01), Kong et al.
patent: 5210051 (1993-05-01), Carter, Jr.
patent: 5393993 (1995-02-01), Edmond et al.
patent: 5523589 (1996-06-01), Edmond et al.
patent: 5670798 (1997-09-01), Schetzina
patent: 5760426 (1998-06-01), Marx et al.
patent: 6146916 (2000-11-01), Nanishi et al.
patent: 6177688 (2001-01-01), Linthicum et al.
patent: 6211095 (2001-04-01), Chen et al.
patent: 6218280 (2001-04-01), Kryliouk et al.
patent: 6218680 (2001-04-01), Carter, Jr. et al.
patent: 6265289 (2001-07-01), Zheleva et al.
patent: 6325850 (2001-12-01), Beaumont et al.
patent: 6350666 (2002-02-01), Kryliouk
patent: 6410940 (2002-06-01), Jiang et al.
patent: 6455870 (2002-09-01), Wang et al.
patent: 6570192 (2003-05-01), Davis et al.
patent: 6649287 (2003-11-01), Weeks et al.
patent: 6775314 (2004-08-01), Waldrip et al.
patent: 6818061 (2004-11-01), Peczalski et al.
patent: 6841001 (2005-01-01), Saxler
patent: 6906351 (2005-06-01), Kryliouk et al.
patent: 6967355 (2005-11-01), Kryliouk et al.
patent: 7001791 (2006-02-01), Kryliouk et al.
patent: 7078318 (2006-07-01), Jurgensen et al.
patent: 7128786 (2006-10-01), Jurgensen et al.
patent: 7193784 (2007-03-01), Jiang et al.
patent: 7210819 (2007-05-01), Jiang et al.
patent: 2001/0035531 (2001-11-01), Kano et al.
patent: 2002/0074552 (2002-06-01), Weeks, Jr. et al.
patent: 2003/0006409 (2003-01-01), Ohba
patent: 2003/0070610 (2003-04-01), Dadgar et al.
patent: 2003/0111008 (2003-06-01), Strittmatter et al.
patent: 2005/0025909 (2005-02-01), Jurgensen et al.
patent: 2005/0285141 (2005-12-01), Piner et al.
patent: 2005/0285142 (2005-12-01), Piner et al.
patent: 2006/0006500 (2006-01-01), Piner et al.
patent: 2006/0191474 (2006-08-01), Chen et al.
patent: 2006/0249748 (2006-11-01), Piner et al.
patent: 2006/0286782 (2006-12-01), Gaska et al.
patent: 1599032 (2005-03-01), None
patent: 10151092 (2003-05-01), None
patent: 102004034341 (2006-02-01), None
patent: 102004038573 (2006-03-01), None
patent: 884767 (1998-12-01), None
patent: 2 440 484 (2008-01-01), None
patent: 1155630 (1989-06-01), None
patent: 11135832 (1999-05-01), None
patent: 11274079 (1999-07-01), None
patent: 2001044124 (2001-02-01), None
patent: WO 2005050730 (2005-06-01), None
patent: WO 2006/123540 (2006-11-01), None
Able et al. “Growth of crack-free GaN on Si(111) with graded AIGaN buffer layers”Journal of Crystal Growth276:415-418 (2005).
Arulkumaran et al. “Enhancement of breakdown voltage by AIN buffer layer thickness in AIGaN/GaN high-electron-mobility transistors on 4 in. diameter silicon”Applied Physics Letters86:123503-123503-3 (2005).
Arulkumaran et al. “Studies of AIGaN/GaN high-electron-mobility transistors on 4-in. diameter Si and sapphire substrates”Solid-State Electronics49:1632-1638 (2005).
Chang et al. “Effect of Buffer Layers on Electrical, Optical and Structural Properties of AIGaN/GaN Heterostructures Grown on Si”Japanese Journal of Applied Physics45(4A):2516-2518 (2006).
Chen et al. Growth of high quality GaN layers with AIN buffer on Si(111) substrates)Journal of Crystal Growth225:150-153 (2001).
Clos et al. “Wafer curvature in the nonlinear deformation range”phys. stat. sol. (a) 201(11):R75-R78 (2004).
Cong et al. “Design of the low-temperature AIN interlayer for GaN grown on Si (111) substrate”Journal of Crystal Growth276:381-388 (2005).
Contreras et al. “Dislocation annihilation by silicon delta-doping in GaN epitaxy on Si”Applied Physics Letters81(25):4712-4714 (2002).
Dadgar et al. Reduction of stress at the initial stages of GaN growth on Si(111)Applied Physics Letters82(1):28-30 (2003).
Dadgar et al. “MOVPE growth of GAN on Si(111) substrates”Journal of Crystal Growth248:556-562 (2003).
Dadgar et al. “Gallium-nitride-based devices on silicon”phys. stat. sol. (c) 0(6):1940-1949 (2003).
Dadgar et al. “In situ measurements of strains and stresses in GaN heteroepitaxy and its impact on growth temperature”Journal of Crystal Growth272:72-75 (2004).
Davies et al. “Fabrication of GaN cantilevers on silicon substrates for microelectromechanical devices”Applied Physics Letters84(14):2566-2568 (2004).
Davies et al. “Fabrication of epitaxial III-nitride cantilevers on silicon (111) substrates”Journal of Materials Science: Materials In Electronics15:705-710 (2004).
Fehse et al. “Impact of thermal annealing on the characteristics of InGaN/GaN LEDs on Si(111)”Journal of Crystal Growth272:251-256 (2004).
Hu et al. “Microstructure of GaN films grown on Si(111) substrates by metalorganic chemical vapor deposition”Journal of Crystal Growth256:416-423 (2003).
Ikeda et al. “High-performance normally off FET using an AIGaN/GaN heterostructure on Si substrate”Journal of Crystal Growth275:e1091-e1095 (2005).
Ikeda et al. “Normally-off operation GaN HFET using a thin AIGaN layer for low loss switching devices”Mater. Res. Soc. Symp. Proc. 831:E6.5.1-E6.5.6 (2005).
Ishikawa et al. “GaN on Si Substrate with AIGaN/AIN Intermediate Layer”Jpn. J. Appl. Phys. 38:L492-L494 (1999).
Ishikawa et al. “Growth of GaN on 4-inch Si substrate with a thin AIGaN/AIN intermediate layer”phys. stat. sol. (c) 0(7):2177-2180 (2003).
Ishikawa et al. “Improved characteristics of GaN-based light-emitting diodes by distributed Bragg reflector grown on Si”phys. stat. sol. (a) 201(12):2653-2657 (2004).
Ishikawa et al. “Characterization of GaInN light-emitting diodes with distributed Bragg reflector grown on Si”Journal of Crystal Growth272:322-326 (2004).
Jamil et al. “Dislocation Reduction and Structural Properties of GaN layers Grown on N+-implanted ALN/Si (111) Substrates”Mater. Res. Soc. Symp. Proc. 892:0892-FF22-03.1—0892-FF22-03.6 (2006).
Jang et al. “The influence of A1xGa1-xN intermediate buffer layer on the characteristics of GaN/Si(111) epitaxy”Journal of Crystal Growth255:220-226 (2003).
Jang et al. “High-quality GaN/Si(111) epitaxial layers grown with various Al0.3Ga0.7N/GaN superlattices as intermediate layer by MOCVD”Journal of Crystal Growth253:64-70 (2003).
Joblot et al. “Hexagonalc-axis GaN layers grown by metalorganic vapor-phase epitaxy on Si(001)”Journal of Crystal Growth280:44-53 (2005).
Katona et al. “Effect of the Nucleation Layer on Stress during Cantilever Epitaxy of GaN on Si (111)”phys. stat. sol. (a) 194(2):550-553 (2002).
Kim et al. “N-type doping of GaN/Si(111) using Al0.2Ga0.8N/AlN composite buffer layer and Al0.2Ga0.8N/GaN superlattice”Journal of Crystal Growth286:235-239 (2006).
Komiyama et al. “Suppression of crack generation in GaN epitaxy on Si using cubic SiC as intermediate layers”Applied Physics Letters88:091901-1—091901-3 (2006).
Kondo et al. “Series Resistance in n-GaN/AIN
-Si Heterojunction Structure”Japanese Journal of Applied Physics45(5A):4015-4017 (2006).
Krost et al. “GaN-based epitaxy on silicon: stress measurements”phys. stat. sol

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Nitride semiconductor structures with interlayer structures does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Nitride semiconductor structures with interlayer structures, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nitride semiconductor structures with interlayer structures will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4205603

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.