Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2010-03-25
2011-10-25
Sarkar, Asok (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257SE21246, C257SE21309, C257SE21437, C438S724000, C438S757000
Reexamination Certificate
active
08043921
ABSTRACT:
A method of removing silicon nitride over a semiconductor surface for forming shallow junctions. Sidewall spacers are formed along sidewalls of a gate stack that together define lightly doped drain (LDD) regions or source/drain (S/D) regions. At least one of the sidewall spacers, LDD regions and S/D regions include an exposed silicon nitride layer. The LDD or S/D regions include a protective dielectric layer formed directly on the semiconductor surface. Ion implanting implants the LDD regions or S/D regions using the sidewall spacers as implant masks. The exposed silicon nitride layer is selectively removed, wherein the protective dielectric layer when the sidewall spacers include the exposed silicon nitride layer, or a replacement protective dielectric layer formed directly on the semiconductor surface after ion implanting when the LDD or S/D regions include the exposed silicon nitride layer, protects the LDD or S/D regions from dopant loss due to etching during selectively removing.
REFERENCES:
patent: 5496750 (1996-03-01), Moslehi
patent: 7384869 (2008-06-01), Riley et al.
patent: 2006/0094193 (2006-05-01), Horstmann et al.
Kirkpatrick Brian K.
Riley Deborah J.
Brady III Wade J.
Garner Jacqueline J.
Sarkar Asok
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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