Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Multiple layers
Reexamination Certificate
1998-12-18
2001-12-18
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Multiple layers
C438S275000, C438S976000, C438S981000, C438S776000
Reexamination Certificate
active
06331492
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates in general to the field of integrated circuit manufacturing, and more particulary, to the formation of a thin film of nitride by using a nitrogen plasma to allow selectively etching of layers during the formation of integrated circuit components requiring multiple voltages.
BACKGROUND OF THE INVENTION
Without limiting the scope of the invention, its background is described in connection with the manufacture and formation of integrated circuit components for use in the creation of metal oxide semiconductors, as an example.
Heretofore, in this field, the major steps in silicon wafer fabrication have been the use of diffusion, metallization, etching and chemical clean-up steps to form semiconductors. The introduction of thermal oxidation of silicon, the use of lithographic photoresist techniques and etching of the various components using specific and nonspecific chemical agents brought forth the era of the planar processing of semiconductor integrated circuits.
More recently, complementary metal oxide silicon devices (CMOS) have been formed by the growth, deposition and etching of conductive and non-conductive layers taking advantage of chemical-vapor deposition (CVD) and ion implantation techniques. Chemical vapor deposition allowed for the selective and non-selective deposition of, e.g., etch protective overcoats, and of masking material.
In addition to CVD, other common ways for the deposition of conducting or insulation thin films has been the use of vacuum deposition or sputtering. Vacuum deposition and sputtering coat the wafer with a thin film which can, e.g., form an inorganic insulating material when heated in a reactive atmosphere. All three techniques can be used to achieve the deposition of a conducting or insulating layer. The deposited layers may also be used as sacrificial layers for use in the selective etching and formation of an integrated circuit component.
SUMMARY OF THE INVENTION
It has been found, however, that present methods for integrated circuit design and manufacture using silicon nitride layers account for a significant portion of the thermal budget during wafer processing. The thermal budget must be lowered to, e.g., enable scaling of high density integrated circuits. In addition, the large number of high temperature processing steps causes a significant impact on energy consumption and environmental impact of the current methods. The use of large amounts of chemical etching agents to remove these sacrificial layers can contribute to device failure (due, e.g., to mobile ions in the etching agents).
Furthermore, the deposition of thick silicon nitride layers can be required when deep etching of surrounding area is to be accomplished. Due to the thermal expansion of the layer during high temperature steps, mechanical stress resulting from the thick silicon nitride layer can lead to device failure.
What is needed is an improved method for the formation of a nitride layer, that does not require a high temperature deposition step. Also, a need has arisen for a nitride layer that can be selectively deposited without affecting a photoresist layer. Also needed, is a thinner layer (to lessen the mechanical stress otherwise caused within a thick layer at high temperatures) The layer, however, preferably still should be an effective barrier against mobile ions, and be easily removed in subsequent steps when used as a sacrificial layer.
The present invention provides an improved method for creating a nitrided silicon layer, or nitrided layer, which is resistant to oxide etching agents but does not require a high temperature deposition step. Using the present invention, a nitrided layer can be selectively deposited without affecting a photoreslst layer. The method of the present invention can also allow for the deposition of a thin layer that lessens the mechanical stress caused within the layer at high temperatures. The nitrided layer of the present invention can provide an effective barrier against mobile ions, and can be easily removed during subsequent steps when used as, e.g., a sacrificial layer.
More particulary, the present invention is directed to a method of making gate oxides on a silicon wafer surface, for multiple voltage applications, which includes the steps of growing a first oxide layer on at least first and second areas of the wafer surface and exposing the oxide areas to a nitrogen ion containing plasma, wherein the nitrogen ions convert a top layer of the exposed oxide area into a nitrided layer. Next a photoresist is patterned over the first area of the oxide layer, followed by partial etching of the second area of the oxide layer not protected by the photoresist. The photoresist is then stripped and the wafer cleaned prior to etching the remaining oxide from the second area. Etching of the remaining oxide from the second area exposes the wafer surface prior to the growth of a second oxide layer without exposing the bare silicon surface of the wafer to photoresist contaminants.
In one embodiment, a low temperature method for making gate oxides on a silicon wafer surface for dual voltage application comprises the steps of, obtaining a substrate and growing an oxide layer on the substrate. The oxide layer has a surface that is exposed to a nitrogen ion containing plasma, where the nitrogen ions form a nitrided layer on the oxide containing surface that can be used to protect layers underneath the nitrided layer from, for example, selective etching agents. In one embodiment, the portion of the second oxide layer that is etched down after removal of the photoresist is about 40 angstroms before final etching.
More particularly, the silicon oxide layer is maintained at a temperature below 600 degrees Celsius during nitridation of the oxide layer, and in one embodiment the temperature being room temperature. The nitrogen ion plasma can be created by a remote plasma.
The step of exposing the oxide containing surface to a nitrogen ion containing plasma can be further defined as occurring at between about 4 and 12 mTorr, and in one embodiment may be, for example, at about 4 mTorr. The step of exposing the oxide containing surface to a nitrogen ion containing plasma can also be defined as occurring for between about 10 to 90 seconds, in one embodiment the exposure occurring for about 60 seconds. In yet another embodiment, the oxide containing surface can be exposed to a nitrogen ion containing plasma at between about 1000 and 3000 watts. In one embodiment the nitrogen ion containing plasma can be created at about 2000 watts. In yet another embodiment the oxide surface is nitridated for 30 seconds in a 2000 W plasma. During the etching step, in one embodiment, the oxide is etched in a buffered hydrofluoric acid for 100 seconds. Additionally, a silicon layer, such as a polysilicon or amorphous silicon layer can be deposited on the oxide layer after the second oxide growth step. In yet another embodiment, the rate of formation of the nitrided oxide layer is dependent on a substrate bias, where the rate of nitrogen ion implantation into the silicon substrate depends on the voltage difference between the substrate and the plasma.
In yet another embodiment of the invention a low temperature method for making gate oxides on a silicon wafer surface for dual voltage applications comprises the steps of growing a first oxide layer on at least first and second areas of the surface, at least one of the areas is exposed to a nitrogen ion containing plasma, wherein the nitrogen ions convert a top layer of the exposed oxide area into a nitrided layer. A layer of photoresist is patterned over the first area of the oxide layer, followed by partial etching of the second area of the oxide layer not protected by the photoresist. Next, the photoresist is stripped and the silicon wafer cleaned to remove any photoresist contamination. The remaining oxide is etched from the second area of the oxide layer. The nitrided layer over the first area is etched and the wafer surface is then exposed to an oxidating environm
Hattangady Sunil V.
Misium George R.
Brady III Wade James
Estrada Michelle
Fourson George
Garner Jacqueline J.
Telecky , Jr. Frederick J.
LandOfFree
Nitridation for split gate multiple voltage devices does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Nitridation for split gate multiple voltage devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nitridation for split gate multiple voltage devices will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2588206