Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2003-05-19
2004-09-28
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S664000, C438S682000, C438S683000
Reexamination Certificate
active
06797614
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuit (IC) fabrication. More particularly, the present invention relates to a design for and a method of improving silicidation of an IC substrate containing germanium.
BACKGROUND OF THE INVENTION
SMOS processes are utilized to increase transistor (MOSFET) performance by increasing the carrier mobility of silicon, thereby reducing resistance and power consumption and increasing drive current, frequency response and operating speed. Strained silicon is typically formed by growing a layer of silicon on a silicon germanium substrate or layer. Germanium can also be implanted, deposited, or otherwise provided to silicon layers to change the lattice structure of the silicon and increase carrier mobility. Another way to increase transistor performance is by utilizing silicon germanium gates and/or by utilizing raised source and drain regions formed from silicon germanium.
The silicon germanium lattice associated with the germanium substrate is generally more widely spaced than a pure silicon lattice, with spacing becoming wider with a higher percentage of germanium. Because the silicon lattice aligns with the larger silicon germanium lattice, a tensile strain is created in the silicon layer. The silicon atoms are essentially pulled apart from one another. Relaxed silicon has a conductive band that contains six equal valance bands. The application of tensile strength to the silicon causes four of the valance bands to increase in energy and two of the valance bands to decrease in, energy. As a result of quantum effects, electrons effectively weigh 30 percent less when passing through the lower energy bands. Thus, lower energy bands offer less resistance to electron flow.
In addition, electrons meet with less vibrational energy from the nucleus of the silicon atom, which causes them to scatter at a rate of 500 to 1,000 times less than in relaxed silicon. As a result, carrier mobility is dramatically increased in strained silicon compared to relaxed silicon, providing an increase in mobility of 80 percent or more for electrons and 20 percent or more for holes. The increase in mobility has been found to persist for current fields up to 1.5 megavolt/centimeter. These factors are believed to enable device speed increase of 35 percent without further reduction of device size, or a 25 percent reduction in power consumption without reduction in performance.
High levels of germanium at the surface of a wafer can adversely affect the formation of silicide layers. In particular, high concentration of germanium in a top surface of a substrate can adversely affect the formation of silicide layers above the source and drain regions. The germanium concentration at the top surface can be exacerbated by the processing associated with source and drain regions and gate structure formation.
The presence of germanium in a silicon layer can cause germanosilicides to form during the silicidation process. Germanosilicides negatively impact the formation of a silicide region because they have a higher resistance than pure nickel silicide, tungsten silicide, etc. According to one conventional silicidation process, a metal layer, such as a nickel, tungsten, or cobalt layer, is deposited above the silicon germanium substrate. The metal layer is annealed at elevated temperatures to form silicide regions (e.g., nickel silicide, cobalt silicide, tungsten silicide, etc.). In the example of nickel silicide, the nickel reacts with germanium and silicon at the elevated temperatures associated with annealing. The reaction forms pockets of nickel germanium, nickel silicide, and nickel germanium silicide (i.e., the phases are immiscible). The nickel germanium and nickel germanium silicide are referred as to germanosilicides and are undesirable because the resistance of germanosilicides is relatively high and because the agglomeration of separate phases occurs at a lower temperature than normal, resulting in a discontinuous film.
Mehmet C. Ozturk presented investigations of alloys of suicides at the Spring 2002 Materials Research Society (MRS) meeting. The investigations included results relating to platinum (Pt) and nickel (Ni) germanosilicide contacts with respect to heavily positively doped (P+) silicon germanium regions. In addition, zirconium (Zr) was also considered as a contact material. Zirconium contacts can provide a contact-resistivity near 10
−8
ohm-centimeter
2
.
Thus, there is a need for an efficient process for forming silicide wafers on a wafer surface in an SMOS process. Further, there is a need for a system and a method which reduces the effects of germanosilicide and/or agglomeration in silicide regions. Even further, there is a need for a method of siliciding a metal layer which avoids germanosilicides and immiscibility. Yet further, there is a need for a process which reduces the adverse effects of germanium on silicidation processes.
SUMMARY OF THE INVENTION
An exemplary embodiment relates to a method of manufacturing an integrated circuit. The method includes providing a gate structure above a semiconductor substrate that includes a strained material and siliciding the semiconductor substrate. The gate structure is provided between a first source location and a first drain location. The semiconductor substrate is silicided using an alloy that includes at least one of vanadium, tantalum, and tungsten. In certain embodiments, the siliciding step can be performed using a single step annealing process or a two step annealing process.
Another exemplary embodiment relates to a method of manufacturing an ultra-large scale integrated circuit including a transistor. The method includes steps of providing a metal layer on a top surface of a semiconductor substrate or layer and annealing to form at least one silicide region. The semiconductor substrate or layer includes strained silicon material, a silicon/germanium material, or a germanium material. The metal layer is an alloy including at least one of vanadium, tantalum, and tungsten.
Still another exemplary embodiment relates to a process performing a transistor. The process includes forming a gate structure on a substrate or layer and depositing a metal alloy including at least one of vanadium, tantalum and tungsten. The process also includes annealing to form silicide regions on the substrate or layer.
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Besser Paul R.
Ngo Minh V.
Paton Eric N.
Xiang Qi
Advanced Micro Devices , Inc.
Picardat Kevin M.
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