Negative drop voltage generator in semiconductor memory...

Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator

Reexamination Certificate

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C365S201000

Reexamination Certificate

active

06906967

ABSTRACT:
In the negative drop voltage generating apparatus of a semiconductor memory device and the method of controlling a negative voltage generation. The apparatus generates a negative voltage having a level necessary for an operating mode in the semiconductor memory device. The apparatus includes a negative drop voltage generator having first and second output terminals and a voltage separated/integrated unit connected between the first and second output terminals of the negative drop voltage generator. The voltage separated/integrated unit performs a voltage separation and connection so that the negative voltages are generated with individually different levels or with the same level through the first and second output terminals, in response to an applied control signal.

REFERENCES:
patent: 5905682 (1999-05-01), Gans et al.
patent: 6147914 (2000-11-01), Leung et al.
patent: 6535435 (2003-03-01), Tanaka et al.
patent: 6545923 (2003-04-01), Sim et al.
patent: 6643208 (2003-11-01), Yamagata et al.

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