Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
1999-07-07
2001-05-08
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S106000, C438S109000, C438S110000, C438S111000, C438S112000, C438S113000, C438S121000, C438S124000, C438S125000, C438S126000, C438S127000, C438S014000, C438S015000, C438S460000, C438S464000
Reexamination Certificate
active
06228676
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the art of electronic packaging and more particularly to a method of packaging an integrated circuit chip and the resulting structure.
BACKGROUND OF THE INVENTION
As electronic devices become increasingly compact and lightweight, it becomes increasingly desirable to reduce the size of integrated circuit chip (IC chip) packages. In addition to reducing the size of IC chip packages, it is also desirable to simultaneously decrease the manufacturing cost of IC chip packages.
SUMMARY OF THE INVENTION
In accordance with the present invention, a near chip size integrated circuit package, called a CHIPARRAY™ package, is presented. In one embodiment, the package includes an IC chip having a first surface with bonding pads formed thereon. A second surface of the IC chip is mounted to a first surface of an insulating substrate. The first surface of the insulating substrate has first metallizations formed thereon. Each of the bonding pads is electrically connected to a corresponding one of the first metallizations. The IC chip, bonding pads, first metallizations, bond wires and the first surface of the insulating substrate are encapsulated in a layer of encapsulant. The layer of encapsulant has edges which are coincident with edges of the insulating substrate.
Interconnection balls can be formed at bonding locations on a second surface of the insulating substrate. Alternatively, instead of forming interconnection balls, interconnection pads can be formed at the bonding locations. Each of the interconnection balls or interconnection pads are electrically coupled to a corresponding one of the first metallizations.
A package formed in accordance with the present invention is near chip size (i.e. the distance between the edge of the insulating substrate and the IC chip can be as small as 10 mil). Thus, the package is particularly advantageous in applications where limited space for the IC chip package is available such as in disk drive applications.
In accordance with the present invention, a method for fabricating several IC chip packages from a single substrate is also presented. The method includes providing the insulating substrate which has sections with first metallizations formed on a first surface of the insulating substrate. An IC chip is mounted in each of the sections, the IC chips having first surfaces with bonding pads formed thereon. The bonding pads are electrically connected to corresponding ones of the first metallizations with bond wires. The bonding pads, the first surfaces of the IC chips, the first metallizations and the first surface of the insulating substrate are encapsulated in a layer of encapsulant. The layer of encapsulant and the insulating substrate are cut along a periphery of each of the sections to form the plurality of integrated circuit chip packages.
The method can further include forming interconnection balls, or alternatively, interconnection pads at substrate bonding locations on a second surface of the insulating substrate, the interconnection balls or pads being electrically connected to corresponding first metallizations.
Fabricating a plurality of packages simultaneously (in contrast to individually) from a single substrate advantageously reduces handling cost and substrate waste thereby reducing the cost of fabricating each individual package.
These and other objects, features and advantages of the present invention will be more readily apparent from the detailed description of the preferred embodiments set forth below taken in conjunction with the accompanying drawings.
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Glenn Thomas P.
Hollaway Roy D.
Panczak Anthony E.
Amkor Technology Inc.
Niebling John F.
Parsons James E.
Skjerven Morrill
Zarneke David A
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