Narrower erase distribution for flash memory by smaller poly gra

Details Narrower erase distribution for flash memory by smaller poly gra Narrower erase distribution for flash memory by smaller poly gra

1998-03-20

1999-11-09

Booth, Richard

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438594, 438264, H01L 218247

Patent

active

059813393

ABSTRACT:
In one embodiment, the present invention relates to a method of forming a flash memory cell involving the steps of: forming a tunnel oxide on a substrate; forming an in situ phosphorus doped polysilicon layer over the tunnel oxide by low pressure chemical vapor deposition at a temperature between about 610.degree. C. and about 630.degree. C., wherein the in situ phosphorus doped polysilicon layer comprises from about 1.times.10.sup.19 atoms/cm.sup.3 to about 5.times.10.sup.19 atoms/cm.sup.3 of phosphorus; forming an insulating layer over the in situ phosphorus doped polysilicon layer; forming a conductive layer over the insulating layer; etching the in situ phosphorus doped polysilicon layer, the conductive layer and the insulating layer, thereby defining one or more stacked gate structures; and forming a source region and a drain region in the substrate, wherein the source region and the drain region are self-aligned by the stacked gate structures, thereby forming one or more memory cells.

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