Narrow width CMOS devices fabricated on strained lattice...

Details Narrow width CMOS devices fabricated on strained lattice... Narrow width CMOS devices fabricated on strained lattice...

2002-06-19

2004-07-20

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S192000

Reexamination Certificate

active

06764908

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to methods of manufacturing improved performance, narrow width, high operating speed, CMOS devices comprised of one or more of each of NMOS and PMOS transistors, on strained lattice semiconductor substrates, and to improved CMOS devices obtained thereby. More specifically, the present invention relates to methods for fabricating such devices wherein the stress level within the strained lattice semiconductor layer of the NMOS and PMOS portions of the device is differentially adjusted to maximize the respective drive currents.
BACKGROUND OF THE INVENTION
The escalating requirements for high density and performance associated with ultra-large-scale integration (ULSI) semiconductor devices require design features of 0.18 &mgr;m and below, e.g., such as 0.15 &mgr;m and 0.12 &mgr;m, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput for economic competitiveness. The reduction of design features to 0.18 &mgr;m and below challenges the limitations of conventional semiconductor materials and manufacturing techniques.
A conventional approach for forming a plurality of active devices in or on a common semiconductor substrate, e.g., as in the case of forming CMOS devices comprising at least a pair of PMOS and NMOS transistors in spaced adjacency, involves division of a starting material, i.e., a semiconductor substrate of suitable characteristics, into active regions where the transistors are to be formed, and field dielectric regions that electrically isolate adjacent active regions.
According to current technology utilizing conventional crystalline semiconductor wafers as substrates, the starting material may, for example, comprise a lightly p-doped epitaxial (“epi”) layer of silicon (Si) grown on a heavily-doped, crystalline Si substrate. The low resistance of the heavily-doped substrate is necessary for minimizing susceptibility to latch-up, whereas the light doping of the epi layer permits independent tailoring of the doping profiles of both the p-type and n-type wells formed therein as part of the fabrication sequence, thereby resulting in optimal PMOS and NMOS transistor performance.
The use of the very thin epi layers, i.e., several &mgr;m thick, is made possible by performing the isolation processing by means of shallow trench isolation (“STI”) techniques rather than by high temperature local oxidation of silicon (“LOCOS”) technology. The STI technique advantageously minimizes up-diffusion of p-type dopant(s) from the more heavily-doped substrate into the lightly-doped epi layer. In addition, and critical for fabrication of devices with design rule of 0.25 &mgr;m and below, STI allows for closer spacing of adjacent active areas by avoiding the “bird's beak” formed at the edge of each LOCOS isolation structure. STI also provides better isolation by creating a more abrupt structure, reduces the vertical step from active area to isolation to improve gate lithography control, eliminates the high temperature field oxidation step that can cause problems with large diameter, i.e., 8 inch, wafers, and is scalable to future logic technology generations.
Recently, there has been much interest in various approaches with the aim or goal of developing new semiconductor materials which provide increased speeds of electron and hole flow therethrough, thereby permitting fabrication of semiconductor devices, such as integrated circuit (IC) devices with higher operating speeds, enhanced performance characteristics, and lower power consumption. One such material which shows promise in attaining the goal of higher device operating speeds is termed “strained silicon”.
According to this approach, a very thin, tensilely strained, crystalline silicon (Si) layer is grown on a relaxed, graded composition Si—Ge buffer layer several microns thick, which Si—Ge buffer layer in turn is formed on a suitable crystalline substrate, e.g., a Si wafer or a silicon-on-insulator (SOI) wafer. Strained Si technology is based upon the tendency of the Si atoms, when deposited on the Si—Ge buffer layer, to align with the greater lattice constant (spacing) of the Si and Ge atoms therein (relative to pure Si). As a consequence of the Si atoms being deposited on a substrate (Si—Ge) comprised of atoms which are spaced further apart, they “stretch” to align with the underlying Si and Ge atoms, thereby “stretching” or tensilely straining the deposited Si layer. Electrons and holes in such strained Si layers have greater mobility than in conventional, relaxed Si layers with smaller inter-atom spacings, i.e., there is less resistance to electron and/or hole flow. For example, electron flow in strained Si may be up to about 70% faster compared to electron flow in conventional Si. Transistors and IC devices formed with such strained Si layers can exhibit operating speeds up to about 35% faster than those of equivalent devices formed with conventional Si, without necessity for reduction in transistor size.
However, a problem exists with respect to the design and fabrication of optimal performance CMOS devices comprised of at least one pair of narrow-width (W) PMOS and NMOS transistors less than about 1 &mgr;m wide utilizing strained lattice semiconductor substrates. Specifically, it has heretofore been difficult to manufacture narrow-width CMOS devices based on strained lattice semiconductor substrates wherein the drive currents of the PMOS and NMOS transistor components thereof are simultaneously maximized. Consider the following apparent competing characteristics or tendencies of narrow-width PMOS and NMOS transistors:
(1) when PMOS and NMOS transistors are fabricated with narrow widths (i.e., <1 &mgr;m) utilizing STI methodology for segmentation of the substrate into active regions where the transistors are to be formed, a compressive stress is exerted on the upper stratum or layer of the adjacent active device regions of the segmented semiconductor substrate spaced apart by the STI region, arising from the insulative material, typically a silicon oxide, filling the STI trench. As a consequence, the drive current of a narrow width PMOS transistor fabricated on or within an active device area subject to such compressive stress is increased, relative to a similar-dimensioned PMOS transistor formed on or within an unstressed semiconductor substrate, whereas the drive current of a narrow width NMOS transistors fabricated on or within the active device area subject to such compressive stress is decreased, relative to a similar-dimensioned NMOS transistors formed on or within an unstressed semiconductor substrate; and
(2) the drive current of a PMOS transistor fabricated on or within a tensilely stressed active device area formed in a strained lattice semiconductor substrate, e.g., strained Si on Si—Ge, is decreased, relative to a similar dimensioned PMOS transistor formed on or within an unstressed semiconductor substrate, whereas the drive current of an NMOS transistor fabricated on or within a tensilely stressed active device area is increased, relative to a similar-dimensioned NMOS transistor formed on or within an unstressed semiconductor substrate.
Accordingly, and in view of the above-described apparent competing characteristics or tendencies of PMOS and NMOS transistors, there exists a need for improved semiconductor design and manufacturing methodology for fabricating CMOS devices on strained lattice semiconductor substrates comprised of narrow-width constituent PMOS and NMOS transistors, which methodology recognizes the above competing effects on the PMOS and NMOS drive currents. Moreover, there exists a need for improved methodology for CMOS device fabrication on strained lattice semiconductor substrates which is fully compatible with conventional process flow for automated manufacturing at rates consistent with the requirements for economic competitiveness.
The present invention, wherein the level of tensile stress in the strained semiconductor layer segments forming active regions for PMOS and NMOS transistors are di

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