Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2003-07-08
2004-11-02
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S596000
Reexamination Certificate
active
06812119
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to transistors and, more particularly, to fin field effect transistors (FinFETs).
BACKGROUND ART
The escalating demands for high density and performance associated with ultra large scale integration semiconductor devices require design features, such as gate lengths, below 100 nanometers (nm), high reliability and increased manufacturing throughput. The reduction of design features below 100 nm challenges the limitations of conventional methodology.
For example, when the gate length of conventional planar metal oxide semiconductor field effect transistors (MOSFETs) is scaled below 100 nm, problems associated with short channel effects, such as excessive leakage between the source and drain, become increasingly difficult to overcome. In addition, mobility degradation and a number of process issues also make it difficult to scale conventional MOSFETs to include increasingly smaller device features. New device structures are, therefore, being explored to improve FET performance and allow further device scaling.
Double-gate MOSFETs represent structures that have been considered as candidates for succeeding existing planar MOSFETs. In double-gate MOSFETs, two gates may be used to control short channel effects. A FinFET is a recent double-gate structure that exhibits good short channel behavior. A FinFET includes a channel formed in a vertical fin. The FinFET structure may be fabricated using layout and process techniques similar to those used for conventional planar MOSFETs.
DISCLOSURE OF THE INVENTION
Implementations consistent with the present invention provide an exemplary process for forming double fins for a double-gate FinFET. The exemplary process, consistent with the invention, improves short-channel effects in the FinFET by thinning the double fins to create narrow fins using, for example, a thermal oxidation process. The exemplary double fin formation process may also, consistent with the invention, increase the device density, thus, reducing the pitch.
Additional advantages and other features of the invention will be set forth in part in the description which follows and, in part, will become apparent to those having ordinary skill in the art upon examination of the following, or may be learned from the practice of the invention. The advantages and features of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of forming fins for a double-gate fin field effect transistor (FinFET). The method includes forming a second layer of semi-conducting material over a first layer of semi-conducting material and forming double caps in the second layer of semi-conducting material. The method further includes forming spacers adjacent sides of each of the double caps and forming double fins in the first layer of semi-conducting material beneath the double caps. The method also includes thinning the double fins to produce narrow double fins.
According to another aspect of the invention, a method of forming fins for a double-gate fin field effect transistor (FinFET) is provided. The method includes depositing a silicon layer over a buried oxide layer and depositing a Si
3
N
4
layer over the silicon layer. The method further includes etching the Si
3
N
4
layer to form double caps, wherein each of the double caps comprises a rectangular cross-section with a width ranging from about 100 Å to about 1000 Å, and depositing and etching an oxide material to form spacers adjacent sides of each of the double caps, wherein the oxide material includes SiO or SiO
2
. The method also includes etching the silicon layer to form fins beneath each of the double caps and thermally oxidating the fins to thin the fins so as to produce narrow fins, wherein each of the narrow fins has a thickness ranging from about 50 Å to about 500 Å.
Other advantages and features of the present invention will become readily apparent to those skilled in this art from the following detailed description. The embodiments shown and described provide illustration of the best mode contemplated for carrying out the invention. The invention is capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings are to be regarded as illustrative in nature, and not as restrictive.
REFERENCES:
patent: 6583469 (2003-06-01), Fried et al.
patent: 6630388 (2003-10-01), Sekigawa et al.
patent: 6642090 (2003-11-01), Fried et al.
patent: 6645797 (2003-11-01), Buynoski et al.
patent: 6657252 (2003-12-01), Fried et al.
patent: 6657259 (2003-12-01), Fried et al.
patent: 6706571 (2004-03-01), Yu et al.
patent: 6709982 (2004-03-01), Buynoski et al.
patent: 2003/0042531 (2003-03-01), Lee et al.
patent: 2004/0048424 (2004-03-01), Wu et al.
Copy of U.S. Ser. No. 10/699,887; filed Nov. 4, 2003; entitled: “Self Aligned Damascene Gate,” 35 pages.
Co-pending U.S. application Ser. No. 10/348,910 filed Jan. 23, 2003 entitled: “Narrow Fin FinFet,” 16 page specification, 13 sheets of drawings.
Digh Hisamoto et al., “FinFET-A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
Yang-Kyu Choi et al., “Sub-20nm CMOS FinFET Technologies,” 2001 IEEE, IEDM, pp. 421-424.
Xuejue Huang et al., “Sub-50 nm P-Channel FinFET,” IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
Xuejue Huang et al., “Sub 50-nm FinFET: PMOS,” 1999 IEEE, IEDM, pp. 67-70.
Yang-Kyu Choi et al., “Nanoscale CMOS Spacer FinFET for the Terabit Era,” IEEE Electron Device Letters, vol. 23, No. 1, Jan. 2002, pp. 25-27.
Copy of co-pending U.S. Application Ser. No. 10/830,006 filed Apr. 23, 2004 entitled: “Narrow Fin Finfet,” 15 page specification, 13 sheets of drawings.
Ahmed Shibly S.
Lin Ming-Ren
Wang Haihong
Yu Bin
Advanced Micro Devices , Inc.
Harrity&Snyder, LLP
Lindsay Jr. Walter L.
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