Narrow bitline using Safier for mirrorbit

Details Narrow bitline using Safier for mirrorbit Narrow bitline using Safier for mirrorbit

2005-03-29

2005-03-29

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having junction gate

C438S526000

Reexamination Certificate

active

06872609

ABSTRACT:
A technique for forming at least part of an array of a dual bit memory core is disclosed. A Safier material is utilized in the formation process to reduce the size of buried bitlines in the memory, which is suitable for use in storing data for computers and the like. The smaller (e.g., narrower) bitlines facilitate increased packing densities while maintaining an effective channel length between the bitlines. The separation between the bitlines allows dual bits that are stored above the channel within a charge trapping layer to remain sufficiently separated so as to not interfere with one another. In this manner, one bit can be operated on (e.g., for read, write or erase operations) without substantially or adversely affecting the other bit. Additionally, bit separation is preserved and leakage currents, cross talk, as well as other adverse effects that can result from narrow channels are mitigated, and the memory device is allowed to operate as desired.

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Solid State Technology's WaferNEWS, The Semiconductor Equipment and Materials Weekly Briefing, Mar. 17, 2003, V10n22, 11 pgs.

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