Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed
Reexamination Certificate
2001-01-05
2002-06-11
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
Electrical characteristic sensed
C438S014000, C438S707000, C438S710000, C438S719000, C438S967000, C438S977000, C324S500000, C324S527000, C324S537000, C324S750010, C324S754120, C324S754120, C324S765010
Reexamination Certificate
active
06403388
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices and their fabrication and, more particularly, to semiconductor devices and their manufacture involving techniques for analyzing and debugging circuitry within an integrated circuit.
BACKGROUND OF THE INVENTION
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
As the manufacturing processes for semiconductor devices and integrated circuits increase in difficulty, methods for testing and debugging these devices become increasingly important. Not only is it important to ensure that individual chips are functional, it is also important to ensure that batches of chips perform consistently. In addition, the ability to detect a defective manufacturing process early is helpful for reducing the number of defective devices manufactured.
To increase the number of pad sites available for a die, different chip packaging techniques have been used. One technique is referred to as a dual in-line package (DIP), in which bonding pads are along the periphery of the device. Another technique, called controlled-collapse chip connection or flip chip packaging, uses the bonding pads and metal (solder) bumps. The bonding pads need not be on the periphery of the die and hence are moved to the site nearest the transistors and other circuit devices formed in the die. As a result, the electrical path to the pad is shorter. Electrical connections to the package are made when the die is flipped over the package with corresponding bonding pads. Each bump connects to a corresponding package inner lead. The resulting packages have a lower profile and have lower electrical resistance and a shortened electrical path. The output terminals of the package may be ball-shaped conductive-bump contacts (usually solder or other similar conductive material) and are typically disposed in a rectangular array. These packages are occasionally referred to as “Ball Grid Array” (BGA). Alternatively, the output terminals of the package may be pins, and such a package is commonly known as the pin grid array (PGA) package.
For BGA, PGA and other types of packages, once the die is attached to the package, the backside portion of the die remains exposed. The transistors and other circuitry are generally formed in a very thin epitaxially grown silicon layer on a single crystal silicon wafer of which the die is singulated from. In a structural variation, a layer of insulating silicon dioxide is formed on one surface of a single crystal silicon wafer followed by the thin epitaxially grown silicon layer containing the transistors and other circuitry. This wafer structure is termed “silicon on insulator” (SOI) and the silicon dioxide layer is called the buried oxide layer (BOX). The transistors formed on the SOI structure show decreased drain capacitance, resulting in a faster switch transistor.
The side of the die including the epitaxial layer containing the transistors and the other active circuitry is often referred to as the circuit side of the die or front side of the die. The circuit side of the die is positioned very near the package. The circuit side opposes the backside of the die. Between the backside and the circuit side of the die is single crystalline silicon and, in the case of SOI circuits, also a buried oxide layer. The positioning of the circuit side provides many of the advantages of the flip chip.
In some instances the orientation of the die with the circuit side face down on a substrate may be a disadvantage or present new challenges. For example, when a circuit fails or when it is necessary to modify a particular chip, access to the transistors and circuitry near the circuit side is typically obtained only from the backside of the chip. This is challenging for SOI circuits, since the transistors are in a very thin layer (about 10 micrometers) of silicon covered by the buried oxide layer (less than about 1 micrometer) and the bulk silicon (greater than 500 micrometers). Thus, the circuit side of the flip chip die is not visible or accessible for viewing using optical or scanning electron microscopy.
Post manufacture analysis of SOI flip chip dies having a buried oxide layer (BOX) typically is destructive for various reasons, such as a need to remove substrate from the flip chip back side in order to access the circuitry. Substrate removal can be difficult to achieve and even destructive. For instance, when too much substrate is removed, the circuitry in the die can be damaged. Analysis of SOI flip chips dies during and after manufacture by nondestructive methods adds to the efficiency of the whole process, in that problems are discovered early and solutions are effected with minimal delays. Thus, there is an unmet need for a method of analyzing and testing flip chip BOX die circuit operations without necessarily destroying the die.
SUMMARY
The present invention is directed to a method and system for analyzing a semiconductor device having SOI structure where it is desired to electrically isolate a portion of the device circuitry. The present invention is exemplified in a number of implementations and applications.
According to one such example embodiment, a nanomachining system is used to remove a selected portion of the backside of a semiconductor device having silicon on insulator (SOI) structure. A selected portion of the circuitry is electrically isolated and analyzed for integrity. In this manner, difficulties associated with flip chip analysis, such as those discussed above can be addressed.
The above summary is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description which follow more particularly exemplify these embodiments.
REFERENCES:
Fixed Pattern Probe Card, Accuprobe. http://www.accuprobe.com/technic/pattern.htm.
FIB: A Window Into Another World, Micrion Corporation http://www.micrion.com/b1.html.
Focused Ion Beam Milling System, National Law Enforcement and Corrections Technology Center—West wysiwyg://47/http://www.nlectc.org
lectcwr/fib.html.
Introduction to Focused Ion Beam Systems, Fibics Incorporated http://www.fibics.com/FIBbasics.htm.
Birdsley Jeffrey D.
Bruce Michael R.
Davis Brennan V.
Ring Rosalinda M.
Stone Daniel L.
Advanced Micro Devices , Inc.
Zarneke David A.
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