Nano-size imprinting stamp using spacer technique

Details Nano-size imprinting stamp using spacer technique Nano-size imprinting stamp using spacer technique

2002-01-31

2004-06-01

Norton, Nadine G. (Department: 1765)

Etching a substrate: processes

Etching of semiconductor material to produce an article...

C428S156000, C428S167000, C428S168000, C428S170000

Reexamination Certificate

active

06743368

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to a structure and method of fabricating nanometer sized imprinting stamps using a spacer technique. More specifically, the present invention relates to a structure and method of fabricating nanometer sized imprinting stamps using a spacer technique, wherein the resulting imprinting stamps can occupy substantially all of a surface area of a substrate the imprinting stamps are formed on and wherein the imprinting stamps can have complex shapes that vary among the imprinting stamps.
BACKGROUND OF THE ART
Nano-imprinting lithography is a promising technique for obtaining nano-size (as small as a few tens of nanometers) patterns. A key step in forming the nano-size patterns is to first form an imprinting stamp that includes a pattern that complements the nano-sized patterns.
In
FIG. 1
a
, a prior nano-imprint lithography process includes an imprinting stamp
200
having a plurality of imprint patterns
202
formed thereon. In
FIG. 1
b
, the imprint patterns
202
consists of a simple line and space pattern having a plurality of lines
204
separate by a plurality of spaces
206
between adjacent lines
204
. By pressing (see dashed arrow
201
) the imprinting stamp
200
onto a specially designed mask layer
203
, a thickness of the mask layer
203
is modulated with respect to the imprint patterns
202
(see
FIG. 1
a
) such that the imprint patterns
202
are replicated in the mask layer
203
.
Typically, the mask layer
203
is made from a material such as a polymer. For instance, a photoresist material can be used for the mask layer
203
. The mask layer
203
is deposited on a supporting substrate
205
. Using a step and repeat process, the imprinting stamp
200
is pressed repeatedly onto the mask layer
203
to replicate the imprint patterns
202
in the mask layer
203
and to cover the whole area of the mask layer
203
.
In
FIG. 2
, after the step and repeat process, the mask layer
203
includes a plurality of nano-size impressions
207
that complement the shape of the imprint patterns
202
. Next, in
FIG. 3
, the mask layer
203
is anisotropically etched (i.e. a highly directional etch) to form nano-sized patterns
209
in the mask layer
203
. Typically, the supporting substrate
205
or another layer (not shown) positioned between the mask layer
203
and the supporting substrate
205
serves as an etch stop for the anisotropic etch. Alternatively, the mask layer
203
can serve as an etch mask for an underlying layer (see reference numeral
208
in
FIGS. 7
a
through
7
d
) and the pattern of the nano-size impressions
207
is replicated in the underlayer by a subsequent anisotropic etch process.
In
FIG. 4
a
, the formation of the imprint patterns
202
on the prior imprinting stamp
200
begins by depositing alternating layers of thin film material (
211
,
213
) on a substrate
215
to form a multi-stacked thin film
210
that extends outward of the substrate
215
. The multi-stacked thin film
210
is then sliced into a plurality of discrete segments &Dgr;
S
along a direction shown by dashed arrow S. For example, in
FIG. 4
b
, the substrate
215
can be a wafer of semiconductor material upon which the multi-stacked thin film
210
is deposited. After all layers of the multi-stacked thin film
210
have been deposited, the wafer (i.e. the substrate
215
) is then sliced to form the discrete segments &Dgr;
S
.
In
FIG. 5
a
, a discrete segment &Dgr;
S
includes a portion of the multi-stacked thin film
210
and a portion of the substrate
215
. In
FIGS. 5
b
and
5
c
, the discrete segment &Dgr;
S
is selectively etched to define the imprint pattern
202
. Differences in etch rates between the alternating layers (
211
,
213
) causes one of the layers to be etched at a faster rate than the other layer resulting in differences in height between the alternating layers (
211
,
213
). Those differences in height define the imprint pattern
202
.
One disadvantage of the prior imprinting stamp
200
is the imprint pattern
202
is formed on only a fraction of the useable area of the imprinting stamp
200
as illustrated in
FIGS. 5
b
,
5
c
, and
6
. The imprint pattern
202
occupies an imprint area I
A
that is substantially smaller than a non-patternable area N
A
. As a result, only a fraction of the available area is utilized by the imprint pattern
202
.
A second disadvantage of the prior imprinting stamp
200
is the imprint pattern
202
consists of simple line and space patterns (
204
,
206
) as is illustrated in FIG.
6
. Consequently, the resulting nano-size impressions
207
are also limited to simple line and space patterns because they complement the imprint pattern
202
.
In
FIG. 7
a
, the imprint stamp
200
is pressed
201
onto the mask layer
203
to replicate the simple line
204
and space
206
patterns of the imprint pattern
202
in the mask layer
203
. In
FIG. 7
b
, after the pressing step, the mask layer
203
includes the complementary nano-size impressions
207
replicated therein. As was noted above, the nano-size impressions
207
also have the simple line and space pattern denoted as
204
′ and
206
′ respectively.
In
FIG. 7
c
, the mask layer
203
is anisotropically etched until the space patterns
206
′ are coincident with an upper surface
208
′ of an underlayer
208
and the line patterns
204
′ extend outward of the upper surface
208
′. The line and space patterns (
204
′,
206
′) will serve as an etch mask for a subsequent anisotropic etch step. Next, in
FIG. 7
d
, the underlayer
208
is anisotropically etched through the mask created by the line and space patterns (
204
′,
206
′) to define the nano-size patterns
209
.
Another disadvantage of the prior imprinting process as illustrated in
FIGS. 7
a
through
7
d
is that the imprint area I
A
and the non-patternable area N
A
of the imprint stamp
200
are replicated in the nano-size patterns
209
such that the only a small fraction of the available area of the substrate
205
is includes the nano-size patterns
209
as indicated by a patterned area P
A
and a large portion of the substrate
205
remains as an unpatterned area U
A
. For example, the patterned area P
A
can be several microns and the unpatterned area U
A
can be several hundred microns or more.
Although, a step and repeat process can be used to repeatedly press the imprint pattern
202
over a larger area of the mask layer
203
, that process can result in print defects caused by some of the material from the mask layer
203
adhering to the imprint patterns
202
or by wear to the imprint patterns
202
due to repeated pressing steps. Moreover, the step and repeat process does not address the limitations created by the aforementioned simple line and space patterns (
204
,
206
).
Consequently, there exists a need for a nano-size imprinting stamp that can be formed over a large area. There is also a need for a nano-size imprinting stamp that can include complex patterns and shapes.
SUMMARY OF THE INVENTION
The nano-size imprinting stamp of the present invention solves the aforementioned disadvantages and limitations. The wide-area nano-size imprinting stamp of the present invention includes a plurality of imprint stamps that can occupy substantially all of a useable surface area of a substrate thereby solving one of the disadvantages of the prior imprint stamps in which the imprint patterns were formed on only a fraction of the useable area available. The imprint stamps of the present invention have complex predetermined shapes that can vary among the imprint stamps so that the limitations of simple line and spaces patterns of the prior imprint stamps are solved. Moreover, the imprinting stamp of the present invention can be formed over a wide area so that the disadvantages associated with the non-patternable area of the prior imprint stamps are also solved.
Other aspects and advantages of the present invention will become apparent from the following detailed description, t

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