Nano-meter memory device and method of making the same

Details Nano-meter memory device and method of making the same Nano-meter memory device and method of making the same

2001-08-27

2004-06-15

Booth, Richard A. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S947000

Reexamination Certificate

active

06750100

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to nonvolatile memory, and specifically to a method of manufacturing a nonvolatile memory device having a minimum feature size in the nano-meter range.
BACKGROUND OF THE INVENTION
Conventional flash memory EEPROMS are made using conventional lithography and etching processes. The minimum feature size is limited by the resolution of the lithography portion of the fabrication process, which is approximately 0.1 &mgr;m (10
−7
meters). E-beam lithography may able to define line width as narrow as 0.01 &mgr;m (10
−8
meters), however, the through put is very slow. A manufacturing process having the reliability and throughput of conventional lithography and etching with nearly the resolution of E-beam lithography is therefore desirable.
SUMMARY OF THE INVENTION
A method of forming a memory device includes preparing a substrate having predefined characteristics; forming a first layer set on the substrate, including: building a first forming layer, having first form segments, on the substrate; building placeholder sidewalls on the first form segments wherein the sidewalls have a thickness of between about one nm and 100 nm; building a second forming layer, having second form segments, on the substrate between the placeholder sidewalls; removing the placeholder sidewalls forming vacated areas; and building active devices in the vacated areas.
It is an object of the invention to provide a method of fabricating a ultra high-density nonvolatile memory circuit.
Another object of the invention is to provide integrated circuit fabrication having a feature size in the nano-meter range.
A further object of the invention is to provide integrated circuit devices which have low power consumption.


REFERENCES:
patent: 6355528 (2002-03-01), Ishida et al.

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