Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-03-01
2004-09-28
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S258000, C438S275000, C438S587000
Reexamination Certificate
active
06797570
ABSTRACT:
This application relies for priority upon Korean Patent Application No. 2000-2039, filed on Jan. 17, 2000, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
This invention relates to semiconductor device and methods of fabricating the same and, more particularly, to NAND-type flash memory devices and methods of fabricating the same.
BACKGROUND OF THE INVENTION
Non-volatile memory devices such as flash memory devices do not lose data stored in their memory cells when the electric power supplied to the device is interrupted. Thus, the flash memory device is widely used in memory cards or the like. Flash memory devices are generally of two types: the NAND-type flash memory device and the NOR-type flash memory device.
A cell array region of the NAND-type flash memory device comprises a plurality of strings. The string typically includes a string selection transistor, a plurality of cell transistors and a ground selection transistor, which are serially connected. The drain region of the string selection transistor is connected to a bit line, and the source region of the ground selection transistor is connected to a common source line.
A cell array region of the NOR-type flash memory device contains a plurality of cell transistors, bit lines and common source lines. Here, only one cell transistor is electrically interposed between the bit line and the common source line.
Accordingly, the NAND-type flash memory device has higher integration density and smaller cell current as compared to the NOR-type flash memory device. The cell current corresponds to current flowing through the bit line and the common source line during a read mode. Thus, it is required to increase the cell current of the NAND-type flash memory device more so than it is in the NOR-type flash memory device. This is because the cell current directly affects access time of the flash memory device. As a result, it is required to decrease electrical resistance of the bit line and/or the common source line in order to improve the access time of the NAND-type flash memory device.
FIG. 1
is a top plan view showing a portion of cell array region of a conventional NAND-type flash memory device. Also,
FIG. 2A
is a cross-sectional view along the line I—I of
FIG. 1
, and
FIG. 2B
is a cross-sectional view along the line II—II of FIG.
1
.
Referring to
FIGS. 1
,
2
A and
2
B, an isolation layer
1
a
defining a plurality of active regions
1
is formed at a predetermined region of a semiconductor substrate
10
. The active regions
1
are defined in parallel to each other. A string selection line pattern
2
s
, first to n
th
word line patterns WP
1
to WPn, and a ground selection line pattern
2
g
are formed across the isolation layer
1
a
and the active regions
1
. Impurity regions
7
,
7
d
and
7
s
are formed at the active regions
1
among the string selection line pattern
2
s
, the first to n
th
word line patterns WP
1
to WPn, and the ground selection line pattern
2
g
. Here, the impurity region
7
d
formed at one side of the string selection line pattern
2
s
acts as a drain region of the string selection transistor. Also, the impurity region
7
s
formed at one side of the ground selection line pattern
2
g
acts as a source region of the ground selection transistor.
Accordingly, the string selection transistor is formed at a portion at which the string selection line pattern
2
s
and the active region
1
intersect each other. Similarly, the ground selection transistor is formed at a portion at which the ground selection line pattern
2
g
and the active region
1
intersect each other. Also, the cell transistors are formed at portions at which the word line patterns WP
1
to WPn and the active region
1
intersect each other. As a result, a string is formed at each active region
1
. Here, the string includes the string selection transistor, the cell transistors and the ground selection transistor that are serially connected.
A first interlayer insulating layer
4
is formed on the entire surface of the substrate including the strings. The first interlayer insulating layer
4
is patterned to form common source line contact holes
3
exposing the respective source regions
7
s
. A conductive layer filling the common source line contact holes
3
, e.g., a doped polysilicon layer, is then formed on the first interlayer insulating layer
4
. The conductive layer is patterned to form a common source line
5
covering the common source line contact holes
3
. The common source line
5
is electrically connected to the source regions
7
s
through the common source line contact holes
3
.
The common source line
5
and the first interlayer insulating layer
4
are covered with a second interlayer insulating layer
6
. The second interlayer insulating layer
6
and the first interlayer insulating layer
4
are successively patterned to form bit line contact holes
8
exposing the respective drain regions
7
d
. Bit line contact plugs
8
a
are formed in the respective bit line contact holes
8
. A metal layer is formed on the entire surface of the resultant structure where the bit line contact plugs
8
a
are formed. The metal layer is then patterned to form a plurality of bit lines
9
covering the respective bit line contact plugs
8
a
. The plurality of bit lines
9
cross over the first to n
th
word line patterns WP
1
to WPn.
As described above, according to the conventional technology, the common source line is interposed between the first and second interlayer insulating layers. Thus, the thickness of the common source line should be increased in order to reduce the resistance of the common source line. However, in the event that the thickness of the common source line is increased, the thickness of the second interlayer insulating layer should be also increased in order to enhance the isolation characteristic between the bit lines and the common source line. At this time, the aspect ratio of the bit line contact holes penetrating the first and second interlayer insulating layers is increased. As a result, it is required to minimize the resistance of the common source line as well as the aspect ratio of the bit line contact holes.
SUMMARY OF THE INVENTION
It is therefore a feature of the present invention to provide a NAND-type flash memory device having low resistance in a common source line as well as low aspect ratio of the bit line contact holes. It is another feature of the present invention to provide methods of fabricating a NAND-type flash memory device, which can minimize the aspect ratio of the bit line contact holes and the resistance of the common source line.
These and other features of the present invention may be provided by a NAND-type flash memory device according to the invention. The device of the invention includes a plurality of isolation layers formed at predetermined regions of a semiconductor substrate and running parallel with each other. A string selection line pattern and a ground selection line pattern cross over active regions between the plurality of isolation layers. The string selection line pattern and the ground selection line pattern run parallel with each other. A plurality of word line patterns is disposed between the string selection line pattern and the ground selection line pattern. Source regions are formed at the active regions adjacent to the ground selection line patterns. The source regions are located opposite the string selection line pattern. Drain regions are formed at the active regions adjacent to the string selection line patterns, the drain regions being located opposite the ground selection line pattern. A common source line is disposed on the source regions and the isolation layers between the source regions, the common source line running parallel with the ground selection line pattern and being electrically connected to the source regions.
A plurality of bit lines are disposed across the plurality of word line patterns and the common source line. The respective bit lines are electrically conn
Hur Sung-Hoi
Oh Heung-Kwun
Park Kyu-Charn
Shin Kwang-Shik
Mills & Onello LLP
Trinh Michael
LandOfFree
NAND-type flash memory devices and methods of fabricating... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with NAND-type flash memory devices and methods of fabricating..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and NAND-type flash memory devices and methods of fabricating... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3213232