NAND memory arrays and methods

Details NAND memory arrays and methods NAND memory arrays and methods

2007-10-02

2007-10-02

Chaudhari, Chandra (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S981000, C257SE21690

Reexamination Certificate

active

10920561

ABSTRACT:
NAND memory arrays and methods are provided. A plurality of first gate stacks is formed on a first dielectric layer that is formed on a substrate of a NAND memory array. The first dielectric layer and the plurality of first gate stacks formed thereon form a NAND string of memory cells of the memory array. A second gate stack is formed on a second dielectric layer that is formed on the substrate adjacent the first dielectric layer. The second dielectric layer with the second gate stack formed thereon forms a drain select gate adjacent an end of the NAND string. The second dielectric layer is thicker than the first dielectric layer.

REFERENCES:
patent: 5149667 (1992-09-01), Choi
patent: 6268251 (2001-07-01), Zhong et al.
patent: 6376876 (2002-04-01), Shin et al.
patent: 2001/0014503 (2001-08-01), Iguchi et al.

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