NAND flash memory devices having 3-dimensionally arranged...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S401000, C257S724000, C257S777000, C257SE27026

Reexamination Certificate

active

07602028

ABSTRACT:
A NAND flash memory device includes a lower semiconductor layer and an upper semiconductor layer located over the lower semiconductor layer, a first drain region and a first source region located in the lower semiconductor layer, and a second drain region and a second source region located in the upper semiconductor layer. A first gate structure is located on the lower semiconductor layer, and a second gate structure is located on the upper semiconductor layer. A bit line is located over the upper semiconductor layer, and at least one bit line plug is connected between the bit line and the first drain region, where the at least one bit line plug extends through a drain throughhole located in the upper semiconductor layer.

REFERENCES:
patent: 5321286 (1994-06-01), Koyama et al.
patent: 6300683 (2001-10-01), Nagasaka et al.
patent: 2004/0125629 (2004-07-01), Scheuerlein et al.
patent: 2005/0263830 (2005-12-01), Wang et al.
patent: 2006/0049449 (2006-03-01), Iino et al.
patent: 10-2004-0058990 (2004-07-01), None
patent: 10-2005-0010260 (2005-01-01), None
patent: 10-2005-0079233 (2005-08-01), None
patent: 1020060057821 (2006-05-01), None

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