NAND flash memory device and method of manufacturing the same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S201000, C438S593000, C438S259000, C257SE21422

Reexamination Certificate

active

07910430

ABSTRACT:
A NAND flash memory device and method of manufacturing the same is disclosed. Source and drain select transistor gates are recessed lower than an active region of a semiconductor substrate. A valid channel length of the source and drain select transistor gates is longer than a channel length of memory cell gates. Accordingly, an electric field between a source region and a drain region of the select transistor can be reduced. It is thus possible to prevent program disturbance from occurring in edge memory cells adjacent to the source and drain select transistors in non-selected cell strings.

REFERENCES:
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patent: 7180121 (2007-02-01), Hieda
patent: 2001/0039091 (2001-11-01), Nakagawa
patent: 2002/0149050 (2002-10-01), Fazio et al.
patent: 2004/0079988 (2004-04-01), Harari
patent: 2005/0090052 (2005-04-01), Matsui et al.
patent: 2006/0023558 (2006-02-01), Cho et al.
patent: 2006/0027855 (2006-02-01), Hur et al.
patent: 1416592 (2003-05-01), None
patent: 1495905 (2004-05-01), None
patent: 2002-176114 (2002-06-01), None
State Intellectual Property Office , The First Office Action, Application No. 2006100941797, Mar. 28, 2008.

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