Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2001-07-23
2002-09-03
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S510000, C438S369000
Reexamination Certificate
active
06444551
ABSTRACT:
BACKGROUND OF THE INVENTION
Dislocation loops and stacking faults within and upon epitaxial silicon cause epitaxial silicon structure issues and poor electrical performance of devices. The devices have a potential risk of higher current leakages and yield losses.
U.S. Pat. No. 5,963,812 to Kataoka et al. describes an oxidation process for an N-type buried layer (antimony).
U.S. Pat. No. 5,034,337 to Mosher et al. and U.S. Pat. No. 5,580,808 to Kataoka et al. describe drive-in/oxidation processes for N-type buried layers (antimony).
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an N-type drive-in method to reduce pits over a buried antimony (Sb) layer.
Another object of the present invention is to provide an N-type drive-in method of buried Sb layers that leads to enhanced epitaxial silicon quality with concomitant improvements in isolated N-channel transistor performance.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a wafer is loaded into an annealing furnace/tool. The wafer having an area of implanted antimony ions. The wafer is annealed a first time at a first temperature in the presence of only a first nitrogen gas flow rate. The wafer is ramped-down from the first temperature to a second temperature in the presence of only an oxygen gas flow rate. The wafer is maintained in the presence of the oxygen gas flow rate at the second temperature. The wafer is ramped-up from the second temperature to a third temperature in the presence of only the oxygen gas flow rate. The wafer is annealed a second time at the third temperature in the presence of only a second nitrogen gas flow rate to drive-in the antimony ions within the area of implanted antimony.
REFERENCES:
patent: 5034337 (1991-07-01), Mosher et al.
patent: 5580808 (1996-12-01), Kataoka et al.
patent: 5587325 (1996-12-01), Comeau
patent: 5963812 (1999-10-01), Kataoka et al.
patent: 6218270 (2001-04-01), Yasunaga
Ku Wen-Yu
Li Ting-Pang
Lu Fang-Cheng
Wang Cheng-Chung
Ackerman Stephen B.
Niebling John F.
Roman Angel
Saile George O.
Stanton Stephen G.
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