N-channel single polysilicon level EPROM cell

Details N-channel single polysilicon level EPROM cell N-channel single polysilicon level EPROM cell

1994-04-25

1995-12-26

Nguyen, Viet Q.

Static information storage and retrieval

Systems using particular element

Semiconductive

257314, 257336, 257327, 257344, 257408, H01L 2504, H01L 2710

Patent

active

054793670

ABSTRACT:
The process provides for the simultaneous N+ type implantation of areas of a semiconductor substrate of type P for the formation of a control gate and of highly doped regions of source and drain, defining a channel region. After oxide growth there is executed the deposition and the definition of a polysilicon layer, one region of which constitutes a floating gate above the control gate and the channel region and partially superimposed over the regions of source and drain.

REFERENCES:
patent: 4649520 (1987-03-01), Boaz
patent: 5229631 (1993-07-01), Woo
patent: 5301150 (1994-04-01), Sullivan
patent: 5307312 (1994-04-01), Maurelli et al.
patent: 5331590 (1994-07-01), Josephson et al.
Yoshikawa et al, "An EPROM Cell Structure for EPLD's Compatible with Single Poly-Si Gate Process".
Julian J. Sanchez et al., "Drain-Engineered Hot-Electron-Resistant Device Structures: A Review" IEEE Transactions on Electron Devices vol. 36, No. 6, 1125-1132, Jun. 1989.
Patent Abstracts of Japan vol. 10, No. 129, (E-403) (2186) May 14, 1986.
Kuniyoshi Yoshikawa et al., "An EPROM Cell Structure for EPLDs Compatible with Single Poly Gate Process" Japanese Journal of Applied Physics: Supplements 18th Int. Conf. on Solid State Devices (1986) Aug. 20-22, Tokyo, Japan.
P. J. Cacharelis et al., "A Modular 1 micron CMOS Single Polysilicon EPROM PLD Technology" Technical Digest of the IEDM, pp. 60-63 San Francisco, Calif.; Dec. 11-14, 1988.
David H. K. Hoe et al., "Cell and circuit Design for Single-Poly EPROM" IEEE Journal of Solid-State Circuits, vol. 24, No.4, pp. 1153-1157 Aug. 1989.

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