Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-09-21
2003-01-07
Hiteshew, Felisa (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S712000, C438S720000
Reexamination Certificate
active
06503843
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the manufacture of integrated circuits on a substrate. More specifically, the present invention relates to a multistep chamber clean process that can be used to improve the gap fill capability of films deposited over the substrate without subjecting the substrate to a potentially damaging plasma.
One of the primary steps in the fabrication of modem semiconductor devices is the formation of a thin film on a semiconductor substrate by chemical reaction of gases. Such a deposition process is referred to as chemical vapor deposition or CVD. Conventional thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions take place to produce a desired film. Plasma enhanced CVD techniques, on the other hand, promote excitation and/or dissociation of the reactant gases by the application of radio frequency (RF) energy to a reaction zone near the substrate surface, thereby creating a plasma. The high reactivity of the species in the plasma reduces the energy required for a chemical reaction to take place, and thus lowers the temperature required for such CVD processes as compared to conventional thermal CVD processes.
CVD techniques may used to deposit both conductive and insulative films during the fabrication of integrated circuits. For applications such as the deposition of insulation films as premetal or intermetal dielectric layers in an integrated circuit, one important physical property of the CVD film is its ability to completely fill gaps between adjacent structures without leaving voids within the gap. This property is referred to as the film's gap fill capability. Gaps that may require filling include spaces between adjacent raised structures such as transistor gates or conductive lines and etched trenches or the like.
As semiconductor device geometries have decreased in size over the years, the aspect ratio of such gaps has dramatically increased. (Aspect ratio is defined as the height of the gap divided by the width of the gap). Gaps having a combination of a high aspect ratio and a small width present a challenge for semiconductor manufacturers to completely fill. In short, the challenge usually is to prevent the deposited film from growing in a manner that closes off the gap before it is filled.
The semiconductor industry is continuously striving to develop new technologies and new film deposition chemistries to address challenges such as the gap fill issue. For example, several years ago some manufacturers switched from a silane-based chemistry for the deposition of intermetal dielectric silicon oxide layers to a TEOS-based (tetraethoxysilane) chemistry. This switch was at least in part due to the improved gap fill capability of the TEOS-based oxide layers. While a TEOS-based chemistry does indeed have improved gap fill capabilities, it too runs up against limitations when required to completely fill sufficiently high aspect ratio, small-width gaps.
One process that the semiconductor industry has developed to improve the gap fill capability of a variety of different deposition processes, including TEOS-based silicon oxide deposition chemistries, is the use of a multistep deposition and etching process. Such a process is often referred to as a deposition/etch/deposition process or “dep/etch/dep” for short. Well known dep/etch/dep processes divide the deposition of the gap fill layer into two or more steps separated by a plasma etch step. The plasma etch step etches the upper corners of the first deposited film more than the film portion deposited on the sidewall and lower portion of the gap thereby enabling the subsequent deposition step to fill the gap without prematurely closing it off. Such dep/etch/dep processes can be performed using either multiple chambers (separate chambers dedicated solely to either the deposition or etch steps) or with a single chamber in an in-situ process. Generally, for any given deposition chemistry, dep/etch/dep processes can be used to fill higher aspect ratio, small-width gaps than a standard deposition step for the particular chemistry would allow.
Another process that the semiconductor industry has developed to address the gap fill issue is the development of high density plasma (HDP) processing CVD techniques. HDP-CVD techniques form a high density plasma at low vacuum pressures and introduce argon or another sputtering agent into the deposition process. The combination of deposition gases and sputtering agent result in a process that simultaneously deposits a film over the substrate and etches the growing film. For this reason, HDP-CVD techniques are sometimes referred to as simultaneous dep/etch processes. HDP-CVD processes generally have improved gap fill capabilities as compared to similar non-HDP-CVD processes.
As integrated circuit feature sizes some of the devices fabricated on the substrate become increasingly sensitive to damage that may be caused by plasma processing techniques including the dep/etch/dep and HDP-CVD techniques described above. This is particularly true as feature sizes are reduced to dimensions of 0.18 microns and less. Thus, some manufacturers attempt to avoid using plasma processing techniques on semiconductor substrates if at all possible.
In addition to depositing a desired film over the substrate, thermal CVD and plasma enhanced CVD deposition techniques typically leave unwanted deposition material on interior surfaces of the deposition chamber including the chamber walls. This unwanted deposition material may be removed with a chamber dry clean operation (also referred to as an in-situ clean operation). Such a dry clean operation is typically performed after the deposition operation is completed and the substrate is removed from the chamber. Etchant gases are then introduced into the chamber to remove the unwanted deposits. The dry clean operation can be a thermal etching process or more commonly a plasma etching process. It can also be done by flowing remotely dissociated etchant atoms into the chamber to etch the deposits. Such dry clean operations can be performed after a CVD film is deposited over a single or after n wafers. The actual frequency of the dry clean operation depends on a number of factors including the chemistry of the CVD process, the length of the process or thickness of film deposited over the substrate and the deposition conditions among other factors.
In view of the above problems with prior art gap fill deposition techniques, new and improved methods of filling gaps are desirable.
SUMMARY OF THE INVENTION
The present invention solves the above described problems associated with previously known deposition processes. The method provides an improved technique of forming a dielectric layer over a substrate disposed in a substrate processing chamber and cleaning deposiition material off the chamber's interior wall and surfaces. The method breaks an in-situ chamber cleaning operation that flows a remotely dissociated etchant gas (e.g., fluorine) into the chamber into two or more separate steps. Typically, previously known chamber cleaning operations that employ such remotely dissociated etchants flow the dissociated atoms into the chamber after deposition of one or more layers within the chamber is completed and without the substrate being present in the chamber. The present invention, however, performs a portion of the chamber cleaning process prior to completing the deposition of the desired layer and with the substrate in the chamber.
According to one embodiment of the present invention, a chamber clean operation is divided into two steps. The first step is done after a portion of the dielectric layer is deposited over the substrate and with the substrate in the chamber. The second step then completes the in-situ chamber cleaning operation and is performed after deposition of the dielectric layer is completed and the substrate has been removed from the chamber. Both the first and second steps of the cleaning operation flow remotely dissociated atoms (preferably fluorine
Xia Li-Qun
Yieh Ellie
Applied Materials Inc.
Hiteshew Felisa
Townsend and Townsend / and Crew LLP
Vinh Lan
LandOfFree
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