Multistage, single-rail logic circuitry and method therefore

Details Multistage, single-rail logic circuitry and method therefore Multistage, single-rail logic circuitry and method therefore

2003-03-13

2004-09-14

Wamsley, Patrick (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C365S233500, C375S355000

Reexamination Certificate

active

06791363

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention concerns multistage, single-rail logic circuitry, and more particularly concerns such circuitry having inter-stage timing elements.
2. Related Art
As computers operate at higher speeds, cycle time of their component logic circuits must decrease. Moreover, the operating speed of the logic circuits must improve disproportionately. That is, as cycle time decreases, the amount of clock skew, latch delay and set up time become a larger portion of each cycle. Since a logic circuit must wait for valid data before evaluating in each cycle, the increasingly large portion of cycle time that must be devoted to clock skew, latch delay and set up time leaves a correspondingly smaller portion of the cycle available for evaluating data. Consequently it presents a very a demanding challenge to design logic circuitry for improved cycle time.
Certain terms are used herein that relate to logic circuitry. The terms “dual-rail” and “single-rail” are used to distinguish between logic circuitry for which each input and output has a respective complementary input and output (“dual-rail logic circuitry”) and logic circuitry which does not necessarily receive a complement for each input nor generate a complement for each output. The term “dynamic logic” is used to refer to logic circuitry that is structured to operate in a sequence of pre-charging and then evaluating. “Static logic” refers to logic circuitry that continuously evaluates whatever is presented to its input or inputs. “Pipelining” or “pipelined” refers to logic connected in a series of stages with a timing mechanism of some sort to control the passing of data from one logic stage to the next, or at least to control the passing of data into or out of a series of logic stages.
Various approaches have been developed to improve logic circuit cycle time.
FIG. 1
illustrates a design for one circuit
100
, according to the prior art. This two-stage, self-timed pipelined logic circuit
100
is implemented with dynamic logic and Mueller-C inter-stage timing elements. More specifically, the pipelined circuit
100
has first and second logic stages
110
and
120
of dual-rail, dynamic logic, with a first Mueller-C inter-stage timing element
118
on the output of the first logic stage
110
and a second Mueller-C element
128
on the output of the second logic stage
120
.
To ensure orderly timing of data from one stage to the next, both of the complementary output lines of the respective logic stages
110
and
120
are coupled to respective NOR gates
114
and
124
in order to detect completion of logic evaluation for the respective stages and to signal the completion to the Mueller-C elements
118
and
128
through interposed inverters
116
and
126
. That is, in its precharge interval, logic stage
110
, for example, is reset by a signal on its reset input, which causes both its output data lines to go low, driving the NOR gate
114
output high and the inverter
116
output, i.e., request input to Mueller-C element
118
, low. Then, when valid data is available at the inputs of the first stage
110
, the request
0
signal to the first stage
110
“reset” input is asserted and the logic
110
responsively evaluates, driving one of the data lines low and the other high. The complementary state of the data drives the NOR gate
114
output low and inverter
116
output high, which drives the Meuller-C element
118
output high, triggeringevaluation of the now valid data on the inputs to the second stage
120
. Once logic stage
120
evaluates, its NOR gate
124
output goes low, which is fed back to the Mueller-C element
118
“ackn” input. Consequently, the Mueller-C element
118
output goes low and resets logic
120
, and so on.
While this circuit
100
is advantageous speed-wise, its logic stages have to be dual-rail so that completion can be detected and signaled from one stage to the next. This is problematic in one respect, since dual-rail logic tends to take up more space than does single-rail logic. Also, the handshaking arrangement of circuitry
100
is complex in some respects. Power consumption may also be an issue with this arrangement.
FIG. 2
illustrates a two-stage, clocked pipeline circuit
200
which addresses some aspects of the limitations of the pipelined circuitry of FIG.
1
. That is, circuitry
200
may be implemented with single-rail, static logic, and with clocked latches, according to the prior art. Specifically, the pipeline circuit
200
has first and second logic stages
220
and
240
of single-rail, static logic, with an input latch
210
and an output latch
250
, clocked by a signal C
2
. Between the logic stages
220
and
240
is a latch
230
, timed by a clock signal C
1
. The latch
230
is referred to as a “mid-cycle” latch because its clock signal C
1
is phase shifted with respect to C
2
, in order to ensure that data does not pass through both logic stages
220
and
240
in a single cycle of clock C
1
. The combination of the mid-cycle latch and the timing of the clock signals C
1
and C
2
ensures orderly data evaluation from one logic stage to the next.
The single-rail aspect of circuitry
200
of
FIG. 2
reduces complexity and the area required for the circuit as compared to the dual-rail circuit
100
of FIG.
1
. Nevertheless, circuit
200
does not have the same speed advantage as the circuit
100
of
FIG. 1
, since circuit
200
is not self-timed and has two latches in the critical path in each clock cycle. Also, the circuits of both
FIGS. 1 and 2
evaluate every clock cycle or upon every request, regardless of whether the input data has changed.
From the above brief discussion of related art, it should be appreciated that further improvements are needed in logic circuitry to improve the trade off between speed and energy consumption.
SUMMARY
The foregoing need is addressed in the present invention, according to which, in an apparatus form of the invention, an apparatus includes first timing circuitry, at least one stage of logic circuitry and second timing circuitry. The first timing circuitry has a first data input and a latch with a latch data input coupled to the first data input and a latch data output coupled to an input of the least one stage of logic circuitry. The second timing circuitry has a latch and an edge detector with respective latch and edge detector data inputs coupled to a data output of the at least one stage of logic circuitry. The edge detector has an output coupled to a control input of the second timing circuitry latch for triggering capture of an output data signal on the data output of the at least one stage of logic circuitry responsive to detecting a signal transition.
Objects, advantages, additional aspects and other forms of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings.


REFERENCES:
patent: 5374894 (1994-12-01), Fong
patent: 5533069 (1996-07-01), Fleek et al.
patent: 6272070 (2001-08-01), Keeth et al.
patent: 6429693 (2002-08-01), Staszewski et al.
patent: 6606361 (2003-08-01), Rowell
patent: 6621883 (2003-09-01), Ton

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