Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1984-09-20
1987-04-21
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365230, 307530, G11C 1140
Patent
active
046601783
ABSTRACT:
An improved row decoding technique for use in a static RAM. Three stages of row decoders are utilized to further decode partially decoded row address signals and combine the decoded signals with a column address signal to enable selected rows of the memory array. To optimize decoding speed, each stage comprises gates which receive only two inputs from the prior stage and the stages are arranged to allow for sharing of signals between adjacent decoders.
REFERENCES:
patent: 3609708 (1971-09-01), Cragon
patent: 3678475 (1972-07-01), Jordan et al.
patent: 3774171 (1971-11-01), Regitz
patent: 4032765 (1977-06-01), Epstein et al.
patent: 4104735 (1978-08-01), Hofmann et al.
patent: 4292548 (1981-09-01), Suarez et al.
Griffus Mike J.
Hardee Kim C.
Fears Terrell W.
Inmos Corporation
Manzo Edward D.
Wise Roger R.
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