Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
1997-04-04
2001-02-27
Whitehead, Jr., Carl (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S048000
Reexamination Certificate
active
06194787
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a carrier for a multistage coupling semiconductor, a semiconductor device using this carrier, and a manufacturing method of this semiconductor device.
2. Description of the Related Art
A semiconductor device coupled at four stages will be described as an example of a prior art. As shown in FIGS.
1
(A) to
1
(D), in case of a first stage E board
11
, the E board
11
has a pattern that among chip selector pads b to e, only pad b is connected to a multistage connection pad
23
by a pattern
21
(see FIG.
1
(A)). Similar to the first stage E board
11
, in case of a second stage F board
12
, the board has a pattern that among chip selector pad b to e, only pad c is connected by a pattern
21
(see FIG.
1
(B)). Similar to the cases of the E and F boards, a third stage G board
13
has a pattern that a connection is made only for pad d (see FIG.
1
(C)), and a fourth stage H board has a pattern that only a connection is made for pad e (see FIG.
1
(D)). Specifically, in the prior art, carriers having different circuit patterns have been manufactured for the first to fourth substrates.
In the foregoing prior art, for example, in the case of the semiconductor device where four stages are coupled, the circuit patterns of the carriers of the boards have been different from first to fourth stages. For this reason, such a semiconductor device has drawbacks in that four kinds of pattern design, glass masks carriers, and electrical characteristic inspections are necessary for the four boards so that cost of the semiconductor device increases. Moreover, when non-defective percentages are different among the circuit patterns of the four boards, the yield percentage of the final product of the semiconductor device is restricted to the value of the lowest non-defective percentage. At the same time, the residual products including defective boards are treated as defective stocks. Moreover, managing cost increases because of variety of kinds of the circuit patterns.
SUMMARY OF THE INVENTION
An object of the present invention, which relates to a circuit pattern of a carrier for a multistage coupling semiconductor, is to provide a carrier for a multistage coupling semiconductor at a lower cost by reduction of the number of circuit patterns, facilitation of management and the like, a semiconductor device using this carrier, and a manufacturing method of this semiconductor device. Specifically, according to the present invention, there is provided a multistage coupling semiconductor carrier which comprises a board and drawing out lines for selecting more than one discrete semiconductor device; wherein the drawing out lines are coupled in parallel.
Namely, the present invention adopts a circuit pattern in which in a carrier of a package for coupling semiconductor devices at a multistage, drawing out lines for selecting individual semiconductor device are coupled in parallel. Thus, the present invention achieves a multistage coupling semiconductor device which can be completed with a circuit pattern of one kind regardless of the number of stages of a multistage.
In order to produce a semiconductor device, each multistage coupling semiconductor carrier having the drawing out lines coupled in parallel is fabricated as a semiconductor device, the drawing out line of the carrier regarded as a non-defective product of a good electrical characteristic after a characteristic inspection is partially cut to conduct multistage coupling. The cutting method is by either laser, sand-blast or etching.
Since a portion of a cut drawing out line of the carrier is not over coated with an insulating material, it can be cut precisely.
Further, since a drawing out line after partial cutting of a pattern of the carrier is coated with an insulating material such as resin, glass, alumina ceramics or the like, the cutting can be preserved.
Namely, according to the present invention, since a circuit pattern of one kind is formed regardless of the number of the multistages, management of one kind of the carrier, one kind of fabrication process and one kind of electrical characteristic inspection can be done easily, which gives the effect of much simplification of the manufacturing process and improvement of yield rate.
REFERENCES:
patent: 5648661 (1997-07-01), Rostoker et al.
patent: 63-318795 (1988-12-01), None
patent: 144040 (1989-09-01), None
Mikubo Kazuyuki
Senba Naoji
Jr. Carl Whitehead
NEC Corporation
Potter Roy
Sughrue Mion Zinn Macpeak & Seas, PLLC
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