Electrical computers and digital data processing systems: input/ – Access arbitrating – Access prioritizing
Patent
1995-06-06
2000-12-12
Follansbee, John A.
Electrical computers and digital data processing systems: input/
Access arbitrating
Access prioritizing
711151, G06F 1318
Patent
active
06161162&
ABSTRACT:
A multiprocessing computer system and method providing multiplexed address and data paths from multiple CPUs to a single storage device. These paths are controlled by an arbitration circuit which allows one CPU to always have the highest priority. The primary CPU may or may not be the highest priority CPU in the arbitration scheme. The arbitration circuit is combined with a controlling mechanism which interfaces to the memory device. This controller operates at a clock rate fast enough to allow the highest priority CPU to access the memory at it's highest data rate and, yet, guarantees a maximum idle period for the lower priority CPU to wait for it's interleaved memory access to complete. A single memory device provides cost and space savings. A controller is responsive to these processors to multiplex their information signals for selectively conveying information present at their address and data ports. A common memory device is addressable by the processors, and responsive to the controller to share addressing of the common memory device.
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Ball Richard D.
Delisle David J.
DeRoo David T.
Fakhruddin Saifuddin
Gauthier Lloyd W.
Follansbee John A.
NEC Corporation
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