Multiport RAM with programmable data port configuration

Details Multiport RAM with programmable data port configuration Multiport RAM with programmable data port configuration

1996-07-29

1998-02-03

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Multiplexing

36518904, 36523005, G11C 1300

Patent

active

057151970

ABSTRACT:
A RAM with programmable data port configuration provides for programmable configuration of RAM data ports, and in the case of a multiport RAM, for independent programmable configuration of each data port. A single programmable RAM cell can be utilized in a variety of data port configurations, thereby reducing the number of combinations necessary in a standard cell library or gate array to implement the every possible configuration. In one embodiment of the invention, a dual port RAM is provided with a decoder, an input multiplexer and an output multiplexer for each data port. The input multiplexer for each data port provides several different selectable mappings of a RAM input word of varying sizes to the input bit lines of the respective data port. Similarly, the output multiplexer for each data port provides several different selectable mappings of the RAM output bit lines to the RAM output word. The decoder receives configuration programming bits to determine the appropriate size of the RAM input and output word for the respective port, and based on column addressing bits, outputs a select signal to select the appropriate mapping from the input and output multiplexers. Decoding circuitry is used during RAM write operations to disable those input bits not addressed.

REFERENCES:
patent: 4633441 (1986-12-01), Ishimoto
patent: 4799053 (1989-01-01), Van Aken et al.
patent: 5117388 (1992-05-01), Nakano et al.
patent: 5195056 (1993-03-01), Pinkham et al.

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