Multiport ram hybrid memory cell with fast write

Details Multiport ram hybrid memory cell with fast write Multiport ram hybrid memory cell with fast write

1987-07-02

1989-05-23

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365154, 36523005, G11C 700

Patent

active

048336483

ABSTRACT:
A fast write CMOS memory cell includes two CMOS inverters connected in a latched configuration with the first CMOS inverter having a P-channel transistor (98) and an N-channel transistor (102) and the second inverter having a P-channel transistor (90) and an N-channel transistor (96). The output of the first inverter is connected to the input of the second inverter with the output of the second inverter connected to the input of the first inverter through a pass transistor (104). The pass transistor (104) is conductive during the static mode of operation and is nonconductive during the write operation. During write, the input of the first inverter is forced to a predetermined logic state with the pass transistor (104) nonconductive. After write, the pass transistor (104) conducts and reconfigures the latch.

REFERENCES:
patent: 4535428 (1985-08-01), Furman
patent: 4719596 (1988-01-01), Bernstein et al.

Affiliated with

Also associated with

Rating

Multiport ram hybrid memory cell with fast write does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiport ram hybrid memory cell with fast write, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiport ram hybrid memory cell with fast write will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1735396