Multiport memory cell circuit having read buffer for reducing re

Details Multiport memory cell circuit having read buffer for reducing re Multiport memory cell circuit having read buffer for reducing re

1997-06-06

1998-08-11

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518904, 36518908, 365190, 36523005, G11C 700

Patent

active

057936811

ABSTRACT:
In order to improve ability for driving the potential of a read bit line (192) to a high level, an output terminal (201b) of a memory circuit (21) and a read word line (182) are connected input terminals (204, 205) of a NAND gate (15) respectively. A gate of a transistor (123) is connected to an output terminal (203) of the NAND gate (15) and its source is connected to a power supply line (111) to be supplied with a VDD potential, while its drain is connected to the read bit line (192). MOS transistors (133, 134) are connected in series between the bit line (192) and a grounding conductor (112). Gates of the transistors (133, 134) are connected to the output terminal (203) and the input terminal (205) of the NAND gate (15) respectively. Thus, a time for converting the output terminal from a low level to a high level is reduced, whereby an access time can be reduced.

REFERENCES:
patent: 5477489 (1995-12-01), Wiedmann
patent: 5477502 (1995-12-01), Hayashi

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