Multiplexing sense amplifier having level shifter circuits

Details Multiplexing sense amplifier having level shifter circuits Multiplexing sense amplifier having level shifter circuits

1993-03-31

1994-12-27

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Multiplexing

36518901, 36518911, 365196, 365202, 327 51, G11C 700

Patent

active

053771435

ABSTRACT:
A memory system comprising a memory array having at least two pairs of data lines, first and second data lines corresponding to columns in the memory array. The memory array also includes two level shifter circuits, a first shifter circuit connected to the first lines and a second level shifter circuit connected to the second data lines, wherein the level shifter circuits produce output signals and may be enabled and disabled. A selection signal is used to selectively enable and disable the level shifter circuits, wherein one pair of data lines may be selected. An amplification circuit is connected to the level shifters for amplifying the output signals from the level shifter circuits, and a logic circuit is used to generate logic output signals in response to the amplified output signals from the amplification circuit.

REFERENCES:
patent: 4984204 (1991-01-01), Sato et al.

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