Multiple word width memory array clocking scheme

Details Multiple word width memory array clocking scheme Multiple word width memory array clocking scheme

1998-01-26

1999-07-27

Mai, Son

Static information storage and retrieval

Read/write circuit

Multiplexing

365219, 365221, 365236, G11C 700

Patent

active

059301767

ABSTRACT:
A circuit for distributing data from a common input source to a number of individual memory cells in a memory array. A multi-bit counter is used to distribute a timing signal to a number of decoder blocks. Each of the decoder blocks receives both a data input signal and the timing signal at all times. When a particular timing signal is present at a given decoder, the input signal containing a fixed width data word is passed through to the corresponding memory array for storing the data word. The present invention reduces the number of internal signal lines necessary to implement the control function and significantly reduces the chip area needed to generate the signal lines.

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