Electronic digital logic circuitry – With test facilitating feature
Reexamination Certificate
2001-04-09
2002-11-12
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
With test facilitating feature
C326S009000, C326S011000, C326S012000, C326S014000
Reexamination Certificate
active
06480019
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention is directed to multiple voted logic cells of integrated circuits, in general, and more particularly, to a multiple voted integrated circuit logic cell testable by a scan chain and a system and method of testing the same.
Generally, in the final design phases of an integrated circuit (IC), a series of scan chains are designed into the IC, preferably by conventional software programs, to permit the fabricator or foundry to test the various logic cells of the manufactured IC as one of the final steps in the production thereof. Conventional scan chains are primarily designed to test individual logic cells, like flip-flops and the like, for example. That is, when a scan chain data signal is applied to a data input of a logic cell and latched by the cell, the scan chain expects the output to respond correctly in order to determine whether or not the cell is faulty. The problem is that multiple voted logic cells by their very design will always respond correctly to a change to a data input thereof, even though one of the individual registers is faulty.
More specifically, a multiple voted logic cell may be comprised of an odd plurality of latching registers configured in parallel with the data input signal of the logic cell coupled to the data inputs thereof. The latching circuits are operated synchronously by a common clock signal to capture and store the same time sample of the input data signal. The data outputs of the latching registers may be coupled to a majority vote circuit which generates the stored signal of the logic cell. If any one of the latching registers is faulty or produces an erroneous output, it will be out-voted by the other two which produce the same and correct output. Accordingly, the storage cell output will always respond correctly to a scan chain data signal, even though one of the individual registers is faulty.
It may be possible to treat the individual registers of the logic cell separately, that is, as individual logic cells themselves, but this would require substantial additional circuitry to each such logic cell at a substantial cost in terms of money, substrate area and possibly performance. But, even if this were possible, this solution would not be able to test the peripheral circuitry to the latching registers of the logic cell, especially the majority vote output circuit, for example. Note that if a fault is passed undetected through the foundry scan chain testing, then only one additional fault in the field operation of the IC may render the logic cell faulty and unusable. Another problem with creating special scan chain testing for these multiple voted logic cells is the substantial new software that would have to be created since the current scan chain testing software is not adequate for testing the individual latching registers of such a logic cell.
Accordingly, it is desirable to provide a multiple voted logic cell design which is testable with the current scan chain software in order to fully test and determine faults within the circuitry of such logic cells. The present invention provides for such a logic cell design and a system and method of testing the same without having to alter substantially the conventional scan chain testing software.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a multiple voted integrated circuit logic cell testable by a scan chain comprises an odd plurality of latching registers, each register having a data input for receiving a scan chain data signal and capable of latching the scan chain data signal and generating an output signal representative thereof; a multiple vote circuit governed by the output signals of said registers for generating an output signal of said logic cell; and circuit means coupled to each latching register for altering selectively the scan chain data signal input thereto.
In accordance with another aspect of the present invention, a scan chain test system is provided for testing at least one multiple voted logic cell of the aforementioned type. The system comprises a scan chain test controller operable to apply the scan chain data signal to the at least one logic cell of an integrated circuit and control the value thereof. The controller is further operable to control the circuit means of the logic cell for altering selectively the scan chain data signal input to each latching register thereof and for receiving and analyzing the logic cell output signals from said at least one logic cell in response to the applied scan chain data signal and the controlled selective alterations thereof to determine a fault in said at least one logic cell.
In accordance with yet another aspect of the present invention, a method of scan chain testing at least one multiple voted logic cell of the aforementioned type is provided. Such method comprises the steps of: applying the scan chain data signal to the data input of each of the latching registers of at least one multiple voted logic cell of said integrated circuit; controlling the value of the applied scan chain data signal; altering selectively the scan chain data signal input to each latching register; and receiving and analyzing the logic cell output signals from said at least one logic cell in response to the applied scan chain data signal and the selective alterations thereof to determine a fault in said at least one logic cell.
REFERENCES:
patent: 4587445 (1986-05-01), Kanuma
patent: 6118297 (2000-09-01), Schenck
patent: 6127864 (2000-10-01), Mavis et al.
Chang Kuo-Chuan
James Robert Ward
Waldie Arthur Howard
Calfee Halter & Griswold LLP
Goodrich Corporation
Rashid James M.
Tran Anh
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