Electronic digital logic circuitry – Three or more active levels
Patent
1998-05-29
2000-10-17
Tokar, Michael
Electronic digital logic circuitry
Three or more active levels
326 59, 326 60, 326112, 326119, 326121, H03K 1900, H03K 19094
Patent
active
061337544
ABSTRACT:
Circuit structure and resulting circuitry for multiple-valued logic. The circuit structure allows the design and fabrication of any r-valued logic function of n-places where r is an integer greater than 1 and n is an integer greater than 0. This structure is called SUpplementary Symmetrical LOgic Circuit structure (SUS-LOC). In circuits incorporating SUS-LOC, circuit branches are realized that uniquely deliver circuit response and output. For some circuits, and due to the operating characteristics of the switch elements, additional circuit elements, or stages, must be incorporated to prevent "back biasing." SUS-LOC is fully active. Only active elements perform logic synthesis and those components not directly related to logic synthesis, such as resistors and/or other passive loads, are relegated the task of circuit protection. The fabrication of r-valued, multi-valued, or multiple-valued logic circuits, designed using the definitions of the SUS-LOC structure can be accomplished with known techniques, materials, and equipment.
REFERENCES:
patent: 3129340 (1964-04-01), Baskin
patent: 3283256 (1966-11-01), Hurowitz
patent: 3492496 (1970-01-01), Callan
patent: 3508033 (1970-04-01), Turecki
patent: 3663837 (1972-05-01), Epstein et al.
patent: 3671764 (1972-06-01), Maley et al.
patent: 3969633 (1976-07-01), Paluck et al.
patent: 4107549 (1978-08-01), Moufah
patent: 4109101 (1978-08-01), Mitani
patent: 4217502 (1980-08-01), Suzuki et al.
patent: 4302690 (1981-11-01), Gollinger et al.
patent: 4704544 (1987-11-01), Horwitz
patent: 4716471 (1987-12-01), Yokomizo
patent: 4737663 (1988-04-01), Varadarajan
patent: 4808854 (1989-02-01), Reinagel
patent: 4990796 (1991-02-01), Olson
patent: 5017817 (1991-05-01), Yamakawa
patent: 5128894 (1992-07-01), Lin
patent: 5200653 (1993-04-01), Moloney et al.
patent: 5398327 (1995-03-01), Yoshida
patent: 5457411 (1995-10-01), Hastings
patent: 5463341 (1995-10-01), Karasawa
patent: 5469163 (1995-11-01), Taddiken
patent: 5512764 (1996-04-01), Seabaugh et al.
patent: 5519393 (1996-05-01), Brandestini
patent: 5548549 (1996-08-01), Ong
patent: 5559734 (1996-09-01), Saito
patent: 5563530 (1996-10-01), Frazier et al.
patent: 5572629 (1996-11-01), Choi
Proceedings, The Twenty-Sixth International Symposium on Multiple-Valued Logic, May 29-31, 1996, Santiago de Compostela, Spain.
Wu, X. W. et al, "CMOS Ternary Logic Circuits," IEE Proceedings, vol. 137, Pt. G, No. 1, Feb. 1, 1990, pp. 21-27.
Ueno, Fumio et al, "Design Method of CMOS Quaternary Threshold Logic Circuits Realized by Multiple Ion Implants," IEEE Proceedings of the Seventeenth International Symposium on Multiple-Valued Logic, Boston, May 26-28, 1987, pp. 268-274.
EDO, LLC
Jordan Andrew S.
Tan Vibol
Tokar Michael
LandOfFree
Multiple-valued logic circuit architecture; supplementary symmet does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multiple-valued logic circuit architecture; supplementary symmet, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple-valued logic circuit architecture; supplementary symmet will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-472798