Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-22
2001-07-10
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S199000, C438S216000, C438S238000, C438S770000, C438S775000, C438S981000
Reexamination Certificate
active
06258673
ABSTRACT:
FIELD OF THE INVENTION
The field of the invention is CMOS integrated circuit processing, in particular processing to produce several thicknesses of gate oxide.
BACKGROUND OF THE INVENTION
Circuit designers often require transistors with different characteristics e.g. high performance, low leakage and/or multiple resistances to high voltage. These different characteristics can be achieved with different gate dielectric film properties and/or thicknesses.
The most common method of forming several thicknesses of gate oxide on the same chip is resist on oxide. However, this method becomes inappropriate when applied to form more than the standard “dual gate” devices.
For example, if a designer wants three gate oxide thicknesses, a standard resist on oxide approach would require 2 intermediate HF etches, 3 oxidations and 2 block level masks. This approach is not only expensive but also forms edge “divots” and planar recess in shallow trench isolation (STI) areas as a consequence of additional oxide etching.
Another method of forming several thicknesses of gate oxide on the same chip is by using nitrogen implantation. The disadvantage of this approach is that the gate thickness differences are dependent on nitrogen implant dose. It is known that too high nitrogen implant dosages degrade gate oxide reliability. Therefore, there is a limitation on gate oxide thickness options for various combinations of devices.
SUMMARY OF THE INVENTION
The invention relates to a method for forming three or four gate thicknesses with only two block level masks.
A feature of the invention is the implantation of ions through the blanket oxide film, which will become the gate interfacial layer of one or more gate dielectric devices.
Another feature of the invention is the implantation of ions in the surface of areas that will have increased and reduced voltage resistance, so that the ion implantation simultaneously accelerates oxide growth in one area and retards oxygen growth in the other area, respectively.
Yet another feature of the invention is the implantation of oxide growth-altering ions through the base oxide in the area that will have non-standard gate oxides while the areas of non-implanted surfaces are protected by a blocking mask; followed by another block mask, stripping the base oxide and growing a new oxide.
Yet another feature of the invention is the implantation of oxide-retarding ions in an area that is to have a thinner than normal gate oxide.
Yet another feature of the invention is the implantation of oxide-promoting ions in an area that is to have an intermediate gate oxide thickness.
Yet another feature of the invention is the use of a blanket ion implant between masks.
Yet another feature of the invention is the implantation of two or more growth altering species in the same area to produce desired dielectric film properties.
These features of the invention result in reduced process steps and complexity compared to prior art methods.
REFERENCES:
patent: 5576226 (1996-11-01), Hwang
patent: 5918116 (1999-06-01), Chittipeddi
patent: 5920779 (1999-06-01), Sun et al.
patent: 6091109 (2000-07-01), Hasegawa
patent: 6110842 (2000-08-01), Okuno et al.
patent: 6133164 (2000-10-01), Kim
Han Liang-Kai
Houlihan Kevin M.
Martin Dale W.
International Business Machines - Corporation
Lytle Craig P.
Petraske Eric W.
Smith Matthew
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