Multiple storage planes read only memory integrated circuit devi

Details Multiple storage planes read only memory integrated circuit devi Multiple storage planes read only memory integrated circuit devi

1996-04-29

1998-02-24

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438588, H01L 218246

Patent

active

057211698

ABSTRACT:
A ROM memory array comprises a doped silicon substrate having a surface with a first array of parallel bitlines formed in the substrate at the surface with an array of channel regions between the bitlines. A dielectric layer is formed on the substrate with a wordline array composed of transversely disposed parallel conductors formed on the dielectric layer, with the bitlines and the channel regions and the wordline array forming an array of field effect transistors. A gate oxide layer is formed over the wordlines. A thin film polysilicon storage plane is formed over the gate oxide layer with a second array of alternating parallel bitlines and channel regions formed in the thin film polysilicon storage plane. The second array of bitlines and channel regions is orthogonally disposed relative to the wordline array and the second array of bitlines is formed in a storage plane over an interpolysilicon oxide dielectric isolation layer. The wordline array and the second array of parallel bitlines and channel regions form an array of thin film transistors.

REFERENCES:
patent: 5358887 (1994-10-01), Hong
patent: 5383149 (1995-01-01), Hong
patent: 5426066 (1995-06-01), Fu et al.
patent: 5429968 (1995-07-01), Koyama

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