Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1993-01-12
1997-04-08
Bowers, Jr., Charles L.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438693, 438672, H01L 21306
Patent
active
056183810
ABSTRACT:
Disclosed is a method for planarizing a metal surface and forming coplanar metal and dielectric layer surfaces with a minimized degree of dishing (metal recess in an oxide cavity or trough) which results from the uneven polishing with a polishing pad. A cavity is formed in a substrate material, such as oxide, and a layer of conductive material such as metal is formed over the cavity and other surfaces of the substrate. Next, a protective layer of material such as silicon dioxide, borophosphosilicate glass (BPSG), silicon nitride, or tetraethylorthosilicate (TEOS), or any insulator or conductor which can be removed at a slower rate than the conductive layer, is formed over the metal surface, the protective layer being not as easily polished as the metal in a chemical mechanical polishing (CMP) process optimized for metal polishing. A first CMP process removes a portion of the protective layer from the underlying metal overburden. A second CMP process, which removes the metal at a greater rate than the protective layer, prevents the polishing pad from dishing metal film in the areas having larger metal features such as large metal buses and bond pads.
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patent: 3841031 (1974-10-01), Walsh
patent: 4193226 (1980-03-01), Gill, Jr. et al.
patent: 4811522 (1989-03-01), Gill, Jr.
patent: 5065273 (1991-03-01), Rajeevakumar
Doan Trung T.
Yu Chris C.
Bowers Jr. Charles L.
Gurley Lynne A.
Micro)n Technology, Inc.
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