Multiple resist layer photolithographic process

Details Multiple resist layer photolithographic process Multiple resist layer photolithographic process

2001-04-13

2003-12-02

Huff, Mark F. (Department: 1756)

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Forming nonplanar surface

C430S312000, C430S313000, C430S328000, C430S394000

Reexamination Certificate

active

06656667

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90105911, filed Mar. 14, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a photolithographic process. More particularly, the present invention relates to a multiple resist layer photolithographic process.
2. Description of Related Art
Due to the increase level of circuit integration, dimensions of circuit devices must be reduced correspondingly. One of the critical steps in the fabrication of integrated circuits fabrication is photolithography. Many processes that are related to the fabrication of a metal-oxide-semiconductor (MOS) device such as thin film patterning and dopant implantation depends on photolithography. More importantly, whether the semiconductor industry is able to fabricated integrated circuits with line width smaller than 0.18 &mgr;m depends very much on further improvement of photolithographic processes in the future.
However, as size of contact openings is reduced to 0.2 &mgr;m and less, step height difference on a silicon wafer between the peripheral circuit region and the device region, having semiconductor devices and conductive structures thereon, has become increasingly critical. Hence, if contact openings need to be simultaneously formed in the peripheral circuit region and the device region, adjusting depth of focus of the photoresist layer in both regions to a similar level becomes very difficult. Consequently, resolution of the photolithographic process is greatly lowered. In addition, consideration regarding the etching selectivity ratio in subsequent etching process, thickness of a photoresist layer cannot be smaller than 0.5 &mgr;m. Therefore, adjusting depth of focus in the device region and the peripheral circuit region simultaneously by lowering photoresist thickness is highly inappropriate.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a multiple resist layer photolithographic process. First, a substrate having an insulation layer and a first photoresist layer sequentially stacked thereon is provided. A first light-exposure is conducted to transfer a pattern on a photomask to the first photoresist layer, thereby forming a first exposure pattern. A post-exposure baking is carried out and then the first photoresist layer is developed. Thereafter, a second photoresist layer is formed over the patterned first photoresist layer. A second photo-exposure is conducted to transfer the pattern on the same photomask to the second photoresist layer, thereby forming a second exposure pattern. The second exposure pattern and the first exposure pattern are aligned. Finally, the second photoresist layer is developed.
Since each of the first and the second photoresist layer has a thickness smaller than 0.5 &mgr;m (between 0.1 to 0.4 &mgr;m), the multi-patterning step can individually adjust thickness of resist in the device region and the peripheral circuit region. Ultimately, depth of focus in both regions will fall within a similar range. Hence, process window and resolution of photolithography can be greatly increased.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


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