Multiple repair size redundancy

Static information storage and retrieval – Read/write circuit – Bad bit

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36523003, G11C 700

Patent

active

060381795

ABSTRACT:
A Random Access Memory including a redundancy scheme wherein redundant memory elements are organized in a mixture of redundancy patches of various sizes, i.e., various number of word/ bit lines in each patch. The number of lines, e.g., 1, 2, 4 or 8 word or bit lines, in each of the patches is selected as appropriate with many different sized patches existing within the same redundancy reservoir. The size the particular patch selected depends on the size of the replaced defect detected during programming.

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patent: 5295101 (1994-03-01), Stephens, Jr. et al.
patent: 5422850 (1995-06-01), Sukegawa et al.
patent: 5487040 (1996-01-01), Sukegawa et al.
patent: 5894441 (1999-04-01), Nakazawa et al.

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