Static information storage and retrieval – Addressing – Multiple port access
Reexamination Certificate
2000-01-28
2001-01-30
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Addressing
Multiple port access
C365S189040, C365S194000, C365S233100, C365S189070
Reexamination Certificate
active
06181634
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a multiple-port semiconductor memory device and, more particularly, to a multiple-port semiconductor memory device, wherein a pair of data, for example, are concurrently read from and written in the memory cell array through an input port and an output port. The present invention also relates to a method for controlling such a-multiple-port semiconductor memory device.
(b) Description of a Related Art
A multiple-port SRAM, typically known as a dual-port SRAM, is generally incorporated as a core macro-block in a LSI. In the general dual-port SRAM, if data are to be read from and written in a single memory cell (or the same address), both the read and write operations are conducted concurrently as in the case of different addresses. In this situation, the read data changes during the read operation from the old data, stored in the memory cell before the write operation, to the new data written into the memory cell after the write operation. This is not preferable because the read data cannot be determined depending on the timing of the read-out.
For solving the above problem, another configuration is also used wherein the write data is first stored in the memory cell and then read therefrom as a read data. However, this operation consumes a larger read time compared to the ordinary read operation in a SRAM. In the dual port SRAM, it is desired that the read and write operations be conducted independently of each other at a higher-speed, especially for the read operation.
For responding to the above request, Patent Publication JP-A-1-285088 proposes a dual-port memory device such as shown in FIG.
1
. In the proposed device, the write data
101
supplied through the input port is bypassed to the output port through a bypass circuit
19
if the read and write operations are to be performed to a single memory cell, wherein both the read address and the write address coincide with each other. This configuration achieves a higher-speed read operation, which is comparable to the read time for the ordinary read operation in a SRAM.
In the mean time, some current dual-port memory device used as a memory macro-blocks includes an input port for the write data and an output port for the read data which are located opposite to each other with the memory cell array sandwiched therebetween. This configuration responds to the request for the increase of the number of bits, or adapts to the structure of a system-on-chip LSI from the view point of chip design. In the system-on-chip LSI, it is desired that the data terminals of the memory macro-block be separated between the input side and the output side thereof. If the bypass circuit shown in
FIG. 1
is incorporated into this type of dual-port memory device, the circuit configuration may be such that shown in FIG.
2
.
FIG. 3
shows a timing chart of the dual-port SRAM of FIG.
2
.
In
FIG. 3
, a timing section
22
of
FIG. 2
generates a read control signal
106
and a write control signal
102
in synchrony with a system clock signal
108
for controlling the input section
16
and the output section
18
. When a comparator (or a coincidence detection section)
17
detects a coincidence between the write address and the read address to generate a coincidence signal
107
, the coincidence signal
107
is delivered to the bypass circuit
19
, which bypasses the write data
101
to the output port as a read data in the clock cycle. In this case, the read operation is conducted at a speed comparable with the speed of the ordinary read operation.
On the other hand, if the write address and the read address do not coincide with each other, the read and write operations are performed to different memory cells independently of each other. In general, the memory cell array has a pair of complementary read bit lines
20
and a pair of complementary write bit lines
21
, with the arrangement such that a non-inverting write bit line and an inverting read bit line are disposed adjacent to each other and an inverting write bit line and a non-inverting read bit line are disposed adjacent to each other. This configuration involves a problem wherein a signal interference occurs between the write data and the read data concurrently appearing on the read bit lines
20
and the write bit lines
21
, respectively. The signal interference delays the read data supplied through the read bit lines
20
compared to the ordinary read operation in a SRAM. This problem is enhanced by the reduction of the line space in the current dual-port SRAM, wherein a coupling capacitance is increased more and more between adjacent bit lines.
The above problem is specifically involved in the arrangement shown in
FIG. 2
, wherein the input port and the output port are opposed to each other with the memory cell array
11
sandwiched therebetween. In the conventional SRAM of
FIG. 1
, this is not the case because there is provided a timing difference between the read operation and the write operation, as shown in
FIG. 4
, wherein the read control signal
102
leads with respect to the write control signal
106
.
SUMMARY OF THE INVENTION
In view of the above, it is an object of the present invention to provide a multiple-port SRAM capable of achieving a higher read operation irrespective of an absence or a presence of coincidence between the write address and the read address even in the case of the arrangement wherein the input port and the output port are opposed to each other with the memory cell array sandwiched therebetween.
The present invention provides a multiple-port memory device comprising a memory cell array including a plurality of memory cells, an input circuit for responding to a write control signal to store a write data to one of the memory cells specified by a write address during a clock cycle of a system clock signal, an output circuit for responding to a read control signal to read a data from one of the memory cells specified by a read address during the same clock cycle, a coincidence detection section for generating a coincidence signal upon coincidence between the read address and the write address, a bypass circuit for responding to the coincidence signal to bypass the write data to the output section, and a timing circuit for responding to the coincidence signal to specify a timing between the write control signal and the read control signal, the timing being such that the read control signal leads with respect to the write control signal upon an absence of the coincidence signal and that the read control signal and the write control signal are generated substantially at the same time upon a presence of the coincidence signal.
In accordance with the multiple-port SRAM of the present invention, the concurrent timing of the read control signal and the write control signal upon generation of the coincidence signal allows the bypass circuit to bypass the write data supplied from the input section to the output section, which deliver the write data as a read data. In addition, the delay of the write control signal enables the output section to read a data from the memory cell specified by the read address without interference between the read data and the write data on the bit lines. The delay of the storage of the write data upon the absence of the coincidence signal does not affect the speed of the computer system so long as the storage is completed in the clock cycle. The high-speed read operation enables the computer system having the dual-port memory device to operate at a higher speed. The timing control between the read control signal and the write control signal based on the coincidence signal is not known in the art.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.
REFERENCES:
patent: 4789960 (1988-12-01), Willis
patent: 5036491 (1991-07-01), Yamaguchi
patent: 5197035 (1993-03-01), Ito
patent: 5321652 (1994-06-01), Ito
patent: 5325332 (1994-0
Dinh Son T.
NEC Corporation
Nguyen Tuan T.
Young & Thompson
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