Multiple pointer memory system

Details Multiple pointer memory system Multiple pointer memory system

1980-10-14

1983-12-06

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365230, G11C 1300

Patent

active

044197462

ABSTRACT:
A memory system includes a multiple memory pointer in which a pointer selection signal selects one of a plurality of memory pointers to generate an address signal for application to the memory for controlling the location of memory operations. In the preferred embodiment the memory is arranged in an X by Y matrix having X times Y individually addressable memory locations. A first pointer circuit has a plurality of address pointers, one of which is selected for generation of an X coordinate address. A second pointer circuit includes a single address pointer for generation of the Y coordinate address. The second pointer circuit may be a multiple pointer in an alternative embodiment. By provision of a number of individually addressable memories responsive to the same memory pointer system, separate application of address signals from differing address pointers to differing memories permits multiple memory operations in a single instruction cycle.

REFERENCES:
patent: 3402398 (1968-09-01), Koerner et al.
patent: 3737879 (1973-06-01), Greene et al.
patent: 3772658 (1973-11-01), Sarlo
patent: 3900837 (1975-08-01), Hunter
patent: 4028675 (1977-06-01), Frankenberg
patent: 4227798 (1980-10-01), Steiner

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