Multiple line buffer type memory LSI

Details Multiple line buffer type memory LSI Multiple line buffer type memory LSI

2001-08-22

2002-07-02

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S230030

Reexamination Certificate

active

06414880

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention broadly relates to a multiple line buffer type memory LSI (Large Scale Integration) in which a plurality of line buffers are added to the memory section. More specifically, this invention is directed to a multiple line buffer type memory LSI which reduces delays in memory access caused by write-back operation from the line buffer to the memory section.
Recently, a great attention has been paid for the multiple line buffer type memory LSI as a technique for achieving higher performance of memory LSIs.
A multiple line buffer type memory LSI is based on a process comprising the steps of adding a multiple line buffer section having a plurality of line buffers to a memory section within a memory LSI, prefetching (previously reading out data) data stored in a memory section to any of the plurality of line buffers, and upon memory access, causing access to the line buffer.
The multiple line buffer type memory LSI has an object to effectively reduce a delay time occurring upon memory access by providing a high-speed-accessible multiple line buffer section as described above.
A typical example of the above-mentioned multiple line buffer type memory LSI is VCM (Virtual Channel Memory) Architecture announced by NEC Corporation. This VCM Architecture is industrialized as a commercial product by the application of 128-Mbit DRAM (Details have been released by NEC Corporation in the name of 128 Mb VC (Virtual Channel) SDRAM Data Sheet.
FIG. 1
is a block diagram illustrating a typical configuration of a related multiple line buffer type memory LSI, schematically showing the block configuration of 128 Mb VC-SDRAM. The conventional multiple line buffer type memory LSI shown in
FIG. 1
will hereinafter be referred to as the related art
1
.
As shown in
FIG. 1
, the related art
1
comprises an address buffer
104
, a command decoder
105
, a control circuit
106
, a memory section
107
, a multiple line buffer section
108
, and a data buffer
109
, and has, as external terminals, an address input terminal group
101
, a command input terminal group
102
and a data input/output terminal group
103
.
A command indicating operational contents in the multiple line buffer type memory LSI is entered into the command input terminal group
102
, and the entered command is decoded by the command decoder
105
and entered into the control circuit
106
.
An address specifying a place where data in this multiple line buffer type memory LSI are stored is entered into the address input terminal group
1
. The entered address is latched by the address buffer
104
and entered into the control circuit
106
.
The control circuit
106
controls the memory section
107
, the multiple line buffer section
108
and the data buffer
109
on the basis of the input from the command decoder
105
and the address buffer
104
.
The memory section
107
includes a row decoder
110
, a memory cell array
111
and a sense amplifying section
112
.
The memory cell array
111
is divided into pages, which are data transfer units, between the memory cell array and the sense amplifying section
112
.
The row decoder
110
selects a page from those in the memory cell array
111
on the basis of the address entered via the address input terminal group
101
. The sense amplifying section
112
activates (amplifies) and retains the page selected by the row decoder
110
.
The multiple line buffer section
108
is provided with a line selector
113
, a column decoder
114
, and one or more line buffers
115
. Herein, it is to be noted that the line buffer may be referred to as a channel in the related art
1
.
Each line buffer
115
is divided into words which are data transfer units between the line buffer and the data buffer
109
.
The row decoder
114
selects a word from those in the line buffer
115
on the basis of the address entered via the address input terminal group
101
, and the line selector
113
controls the respective line buffers
115
.
In the case of an ordinary DRAM (hereinafter referred to as a “page type memory LSI”), data are read out in units of a word from the activated page which is read out into the sense amplifying section.
Herein, it is noted that a typical example of page type memory LSI is SDRAM, the details of which has been published by NEC Corporation as “128 Mb SDRAM Data Sheet”.
By contrast, data for the portion called a segment in an activated page are read and written in a lump with the multiple line buffer section
108
in the case of the VC-SDRAM in the related art
1
shown in FIG.
1
.
Memory access in the related art
1
is carried out by two-stage operations comprising background operations and foreground operations.
In this event, the background operations mean operations necessary for data transfer in units of a segment conducted between the memory section
107
and the multiple line buffer section
108
.
The foreground operations mean data transfer operations in units of a word performed between the multiple line buffer section
108
and the data input/output terminal group
103
.
The background operations mainly comprise the following four operations: a page opening operation (ACT command) for activating the page and reading it out into the sense amplifying section
112
; a prefetch operation (PFC command) for reading out a desired segment from the page read out (activated) into the sense amplifying section
112
in the memory section
107
into the multiple line buffer section
108
; a restore operation (RST command) for writing back the segment into the page read out (activated) into the sense amplifying section
112
in the memory section
107
(RST command); and a page closing operation (PRE command) for preparing for activation by closing the activated page.
On the other hand, the foreground operations mainly includes the following two operations: a buffer read operation (READ command) for reading out a word from a desired line buffer
115
in the multiple line buffer section
108
; and a buffer write operation (WRIT command) for writing words into a desired line buffer
115
.
In the related art
1
, the multiple line buffer section
108
is full-associatively configured. This means that it is possible to read out a segment at an arbitrary position into an arbitrary line buffer
115
.
The following three methods are available for memory access in the related art
1
, varying with data retained in the line buffer
115
.
FIG. 2
is a timing chart illustrating an example of the data read operation in the multiple line buffer type memory LSI shown in FIG.
1
.
1. Hitting case (see FIG.
21
A): This represents a memory access method applicable when there are data to be accessed in the line buffer
115
, and comprises the step of directly accessing (READ) the line buffer
115
storing the data. In this case, memory access can be performed at a high speed.
2. Error case (see FIG.
2
B): A memory access method applicable when data to be accessed are not present in the line buffer
115
, but there is an overwritable line buffer (a line buffer retaining the same data as in the memory
107
, a line buffer not as yet used). This method comprises the steps of transferring the data to be accessed from the memory section to the overwritable line buffer (ACT-PFC), and then, accessing (READ) the line buffer
115
.
3. Write-back case (see FIG.
2
(C)): The memory access method applicable when the data to be accessed are not present in the line buffer
115
and there is no overwritable line buffer, comprising the steps of first preparing an overwritable line buffer by writing back the data of the line buffer
115
into the memory section
107
(RST), then, transferring the data to be accessed from the memory section
107
to the line buffer
115
made overwritable (ACT-PFC), and then, accessing the line buffer
115
(READ).
In the related art
1
, as described above, the aforementioned write-back case necessitates an operation of writing back the data of the line buffer into the memory section, and this data writing-back operation results in a longer de

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