Multiple leadframe laminated IC package

Details Multiple leadframe laminated IC package Multiple leadframe laminated IC package

2002-06-10

2004-05-11

Lebentritt, Michael S. (Department: 2824)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Metallic housing or support

C438S106000, C257S666000, C257S668000

Reexamination Certificate

active

06734044

ABSTRACT:

FIELD OF THE INVENTION
This invention relates in general to integrated circuit packaging, and more particularly to a method for manufacture of an integrated circuit package.
BACKGROUND OF THE INVENTION
High performance integrated circuit (IC) packages are well known in the art improvements in IC packages are driven by demands for increased thermal and electrical performance, decreased size and cost of manufacture.
Typically, array packaging such as ball grid array (BGA) packages provide for a high density package.
FIG. 1
shows a typical prior art package in which a copper leadframe
20
is etched to approximately half the leadframe thickness to form a pocket for the semiconductor die
22
. The etch-down process results in an etch-down pocket with a radius
24
at each pocket corner (where the base
26
on which the semiconductor die
22
is mounted, meets each side
28
). Each IC package includes a pocket that is large enough to accommodate the die
22
and the radius
24
. Thus, the radius
24
limits the reduction in the size of the pocket.
Prior art IC packages such as that shown in
FIG. 1
are manufactured such that each of the contacts lie in a single plane. Thus, the solder ball contacts
30
on the leadframe lie in the same plane as the solder ball contacts
30
on the semiconductor die. The half etch depth of the leadframe
20
is important in order to ensure that all of the solder ball contacts
30
lie in a single plane. The half etch depth Is difficult to accurately control and therefore manufacture of the IC package with solder ball contacts
30
in a single plane is difficult.
Accordingly, it is an object of an aspect of the present invention to provide a method for manufacturing an IC package that obviates or mitigates at least some of the disadvantages of the prior art.
SUMMARY OF THE INVENTION
In one aspect of the present invention there is provided a method of fabricating an integrated circuit package. The method includes providing a first leadframe and a second leadframe laminating the second leadframe to a portion of the first leadframe in order to create a multi-layer laminated leadframe, and mounting a semiconductor die on another portion of the first leadframe.
In another aspect of the present invention there is provided an integrated circuit package. The integrated circuit package includes afirst leadframe, a second leadframe laminated to a portion of the first leadframe in order to create a multi-layer laminated leadframe, and a semiconductor die mounted to another portion of the first leadframe.
In a particular aspect, the IC package of the present invention is manufactured without a large radius in the etch-down pocket of the leadframe strip. Advantageously, this permits reduced overall package size. Also, accurate control over manufacturing processes allows for planarity of the contacts.
In another aspect, the use of the solder contact balls is obviated by the use of solder plating on the leadframe strip. Also, die level solder Lumps are replaced with copper plates. Advantageously, this package provides reduced electrical resistance to the electrical contacts, simpler and more cost effective construction.


REFERENCES:
patent: 6081031 (2000-06-01), Letterman, Jr. et al.
patent: 6555899 (2003-04-01), Chung et al.
patent: 6677672 (2004-01-01), Knapp et al.

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