Multiple internal phase-locked loops for synchronization of chip

Details Multiple internal phase-locked loops for synchronization of chip Multiple internal phase-locked loops for synchronization of chip

1998-01-23

1999-12-28

Heckler, Thomas M.

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

39550013, G06F 112, G06F 1900

Patent

active

060095326

ABSTRACT:
An apparatus and a method for easing design constraints with respect to placement of computer system components and subsystems requiring relative synchronicity are described. In one embodiment, the apparatus includes a first phase-locked loop (PLL) coupled to a reference clock pin by a path of length L1 and a first PLL feedback pin by a path of length L2 such that L1.apprxeq.L2. In another embodiment, the apparatus includes a second PLL coupled to the reference clock pin by a path of length L3. The second PLL is coupled to an internal core of the integrated circuit by a path of length L4 such that L3.apprxeq.L4. In one embodiment, a computer system incorporating the apparatus includes a first propagation path of length L5 coupled to the first PLL output pin. The first PLL output pin is coupled to the first PLL feedback pin by a path of length L6 such that L5.apprxeq.L6. The choice of electrical lengths allows relative synchronicity between the clock signals propagated to the internal core and the end of the first propagation path.

REFERENCES:
patent: 3567914 (1971-03-01), Neese et al.
patent: 5544088 (1996-08-01), Aubertine et al.

Affiliated with

Also associated with

Rating

Multiple internal phase-locked loops for synchronization of chip does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiple internal phase-locked loops for synchronization of chip, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple internal phase-locked loops for synchronization of chip will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2390382