Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-04-27
2003-04-29
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06555437
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to field effect transistor fabrication methods, and more particularly to engineering of the channel under the transistor to counter short field effects in deep-submicron complementary (CMOS) field effect transistors on the same chip.
BACKGROUND ART
When a MOSFET gate length is scaled below approximately 100 nanometers (nm), short channel effects become significant factors. Strong or higher implant dose halo implants are widely used in deep submicron CMOS technology to engineer the FET channel to overcome short channel effects. Strong halo implants, however, tend to degrade channel mobility, resulting in low device drive current. The usual single halo implant is not sufficient to control threshold voltage (V
th
) roll-off at 50 nm or smaller gate lengths. What is needed is a method of engineering the channel doping profile for overcoming the short channel effects in deep submicron CMOS chips having gate lengths of approximately 50 nm or less.
BRIEF SUMMARY OF THE INVENTION
The present invention is a method and device for improving the channel doping profile of deep-submicron field effect transistors and MOSFETs. The method involves creating a multi-graded lateral channel doping profile by dual halo implants annealed at different temperatures to improve the threshold voltage roll-off characteristics of MOSFETs of approximately 50 nm or less.
By way of example, and not of limitation, the method comprises the following steps after formation of the gate stack. A shallow source/drain extension implant is performed. A spacer is then formed on the sidewalls of the gate. A raised source/drain region is formed by selective epitaxy growth. Next, a deep source/drain implant is performed, followed by an anneal at a first temperature range. The spacer is then removed. A first, higher energy, halo is implanted with a small tilt angle through the gap where the spacer was removed, and then annealed at a second temperature range that is generally lower than the first anneal temperature range. A second, lower energy, halo is then implanted with a small tilt angle and then annealed at a third temperature range that is generally lower than the second temperature range. The differential temperature annealing of the halo implants results in a more localized, tightly distributed halo profile, close to the source/drain junction. A second spacer is then formed. The microelectronic chip is then silicided and the MOSFET is further completed. The resultant device operates at an increased speed compared to similar heretofore known devices. The instant method improves device density on the substrate and improves manufacturing precision and efficiency. Other features of the present invention are disclosed or apparent in the section entitled: “DETAILED DESCRIPTION OF THE INVENTION.”
REFERENCES:
patent: 5818098 (1998-10-01), Davies et al.
patent: 6090691 (2000-07-01), Ang et al.
patent: 6114211 (2000-09-01), Fulford et al.
patent: 6248637 (2001-06-01), Yu
patent: 6255178 (2001-07-01), Brown et al.
Jaeger, Richard C. Introduction to Microelectronic Fabrication, vol. V, Addison-Wesley, 1988, p. 125.
Advanced Micro Devices , Inc.
Elms Richard
LaRiviere Grubman & Payne, LLP
Luhrs Michael K.
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