Multiple-gate transistors and processes of making same

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257SE21158, C257SE21421, C257SE29165, C257SE29264, C257SE29275, C257SE29319, C438S179000, C438S283000, C438S286000

Reexamination Certificate

active

08063447

ABSTRACT:
A microelectronic device includes a P-I-N (p+ region, intrinsic semiconductor, and n+ region) semiconductive body with a first gate and a second gate. The first gate is a gate stack disposed on an upper surface plane, and the second gate accesses the semiconductive body from a second plane that is out of the first plane.

REFERENCES:
patent: 6961807 (2005-11-01), Hauck
patent: 7105390 (2006-09-01), Brask et al.
patent: 2007/0069293 (2007-03-01), Kavalieros et al.
patent: 2007/0138533 (2007-06-01), Dennard et al.
Gopalakrishnan et al. (“Impact Ionization MOS (I-MOS)—Part II, Experimental Results”, IEEE transaction on ED, vol. 52 (1), pp. 77-84, Jan. 2005).
Gopalakrishnan et al. (“Impact Ionization MOS (I-MOS)—Part I, Device and Circuit Simulation”, IEEE transaction on ED, vol. 52 (1), pp. 77-84, Jan. 2005).
Doyle et al. (“Tri-gate Fully-depleted CMOS Transistors: Fabrication, Design and Layout”, 2003 Symposium on VLSI Technology, Tokyo, Japanese Soc. Applied Physics, 2003.

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