Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-06-06
2009-10-20
Landau, Matthew C (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S165000, C438S284000, C257SE21014
Reexamination Certificate
active
07605039
ABSTRACT:
Provided are a multiple-gate MOS (metal oxide semiconductor) transistor and a method of manufacturing the same. The transistor includes a single crystalline active region having a channel region having an upper portion of a streamlined shape (∩) obtained by patterning an upper portion of a bulk silicon substrate with an embossed pattern, and having a thicker and wider area than the channel region; a nitride layer formed at both side surfaces of the single crystalline active region to expose an upper portion of the single crystalline active region at a predetermined height; and a gate electrode formed to be overlaid with the exposed upper portion of the single crystalline active region of the channel region.
REFERENCES:
patent: 6342410 (2002-01-01), Yu
patent: 6413802 (2002-07-01), Hu et al.
patent: 6475890 (2002-11-01), Yu
patent: 6495403 (2002-12-01), Skotnicki et al.
patent: 6562665 (2003-05-01), Yu
patent: 6853020 (2005-02-01), Yu et al.
patent: 6884669 (2005-04-01), Chang et al.
patent: 6885055 (2005-04-01), Lee
patent: 7186599 (2007-03-01), Ahmed et al.
patent: 2004/0036127 (2004-02-01), Chau et al.
patent: 2004/0150029 (2004-08-01), Lee
patent: 2004/0222464 (2004-11-01), Shimada
patent: 2005/0104096 (2005-05-01), Lee et al.
patent: 2005/0156202 (2005-07-01), Rhee et al.
patent: 2005/0205944 (2005-09-01), Clark et al.
patent: 2005/0263821 (2005-12-01), Cho et al.
patent: 10 0467527 (2002-12-01), None
patent: 10 0420070 (2003-08-01), None
patent: 10 0458288 (2003-08-01), None
patent: 10 0532564 (2005-11-01), None
‘A Folded-Channel MOSFET for Deep-sub-tenth Micron Era’ Hisamoto et al., Central Research Laboratory, Hitachi, Ltd. et al., pp. 1032-1034 1998 IEEE.
‘Sub 50-nm FinFET: PMOS’ Huang et al., Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, CA, 1999 IEEE, pp. 67-70.
‘FinFET Scaling to 10nm Gate Length’ Chang et al., Strategic Technology, Advanced Micro Devices, Inc., Sunnyvale, CA et al., 2002 IEEE, pp. 251-254.
‘Pi-Gate SOI MOSFET’ Park et al., IEEE Electron Device Letters, vol. 22, No. 8, Aug. 2001, pp. 405-406.
‘35nm CMOS Fin FETs’ Yang et al., 2002 Symposium on VLSI Technology Digest of Technical Papers, 2002 IEEE.
‘Sub-20nm CMOS FinFET Technologies’ Choi et al., Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, CA et al., pp. 421-424 2001 IEEE.
‘Advanced Depleted-Substrate Transistors: Single-gate, Double-gate and Tri-gate (Invited Paper)’ Chau et al., Components Research, Logic Technology Development, Intel Corporation Hillsboro, OR, 2002.
‘25 nm CMOS Omega FETs’ Yang et al., Taiwan Semiconductor Manufacturing Company, Taiwan, 2002 IEEE.
‘Extension and Source/Drain Design for High-Performance FinFET Devices’ Kedzierski et al., IEEE Transactions on Electron Devices, vol. 50, No. 4, Apr. 2003, pp. 952-958.
Cho Young Kyun
Kim Jong Dae
Roh Tae Moon
Electronics and Telecommunications Research Institute
Ladas & Parry LLP
Landau Matthew C
Luke Daniel
LandOfFree
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